Grounding dummy gate in scaled layout design

• US 9,379,058 B2
• Filed: 05/09/2014
• Issued: 06/28/2016
• Est. Priority Date: 02/14/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Song, Stanley Seungchul, Wang, Zhongze, Kwon, Ohsang, Rim, Kern, Zhu, John Jianhong, Chen, Xiangdong, Vang, Foua, Stephany, Raymond George, Yeap, Choh Fei
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US14/274,184
• Publication Number:
  US 20150235948A1
• Time in Patent Office: 781 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2027/11866 Gate electrode terminals or contacts
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42312 Gate electrodes for field effect devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Claims

1. A semiconductor device, comprising:

a dummy gate in a semiconductor device active area;

a first active contact adjacent to the dummy gate;

a first stacked contact electrically coupled to the first active contact and including a first isolation layer on sidewalls electrically isolating the first stacked contact from the dummy gate and a cap layer on a surface of the first stacked contact opposite the first active contact; and

a first via electrically coupled to the dummy gate and landing directly on the surface of the first stacked contact through a portion of the cap layer and directly contacting the first isolating layer on a sidewall of the first stacked contact, the first via arranged to electrically couple the first stacked contact and the first active contact to the dummy gate to ground the dummy gate.

2. The device of claim 1, further comprising:

a gate contact directly coupled between the dummy gate and the first via, the gate contact having a second isolation layer on sidewalls, the gate contact being self-aligned to the first active contact and self-aligned with the first stacked contact.

3. The device of claim 1, further comprising:

a second active contact adjacent to the dummy gate; and

a neighbor stacked contact electrically coupled to and aligned with the second active contact and being self-aligned with the first via to electrically isolate the neighbor stacked contact from the first via.

4. The device of claim 2, in which the first via is self-aligned with the gate contact and the first isolation layer on sidewalls of the first stacked contact is arranged to at least partially overlap the first active contact, an overlapping portion of the first isolation layer electrically isolating a portion of the first stacked contact from a portion of the first via.

5. The device of claim 1, further comprising:

an active gate;

a second active contact adjacent to the active gate;

a second stacked contact electrically coupled to the second active contact and including a second isolation layer on sidewalls electrically isolating the second stacked contact from the active gate; and

a second via electrically coupled to the active gate and being self-aligned with the second stacked contact.

6. The device of claim 1 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

7. A semiconductor device, comprising:

a dummy gate in a semiconductor device active area;

a first active contact adjacent to the dummy gate; and

an extended stacked contact directly electrically coupled to a gate contact of the dummy gate and the first active contact, and directly contacting a portion of an isolation layer between the gate contact and the first active contact, the extended stacked contact arranged to ground the dummy gate by at least partially overlapping both the dummy gate and the first active contact, the extended stacked contact being self-aligned with a neighbor stacked contact to electrically isolate the extended stacked contact from the neighbor stacked contact.

8. The device of claim 7, further comprising:

an active gate;

a second active contact adjacent to the active gate;

a second stacked contact electrically coupled to the second active contact and including a second isolation layer on sidewalls electrically isolating the second stacked contact from the active gate; and

a via electrically coupled to the active gate and being self-aligned with the second stacked contact.

9. The device of claim 7, integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

10. A semiconductor device, comprising:

a dummy gate in a semiconductor device active area;

a first active contact adjacent to the dummy gate;

first means for electrically coupling to the first active contact including a first means for isolating the first electrical coupling means from the dummy gate and a cap layer on a surface of the first electrical coupling means opposite the first active contact; and

a first via electrically coupled to the dummy gate and landing directly on the surface of the first electrical coupling means through a portion of the cap layer and directly contacting the first means for isolating on a sidewall of the first electrical coupling means, the first via arranged to electrically couple the first electrical coupling means and the first active contact to the dummy gate to ground the dummy gate.

11. The device of claim 10, further comprising:

a gate contact directly coupled between the dummy gate and the first via, the gate contact having a second means for isolating on sidewalls, the gate contact being self-aligned to the first active contact and self-aligned with the electrical coupling means.

12. The device of claim 11, further comprising:

a second active contact adjacent to the dummy gate; and

a neighbor electrical coupling means electrically coupled to and aligned with the second active contact and being self-aligned with the first via to electrically isolate the neighbor electrical coupling means from the first via.

13. The device of claim 11, in which the first via is self-aligned with the gate contact and the first isolating means of the electrical coupling means is arranged to at least partially overlap the first active contact, an overlapping portion of the first isolating means electrically isolating a portion of the electrical coupling means from a portion of the first via.

14. The device of claim 10, further comprising:

an active gate;

a second active contact adjacent to the active gate;

second means for electrically coupling to the second active contact and including a third means for isolating the second electrical coupling means from the active gate; and

a second via electrically coupled to the active gate and being self-aligned with the second electrical coupling means.

15. The device of claim 10 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.