Monolithic semiconductor chip array

• US 9,379,161 B2
• Filed: 02/05/2014
• Issued: 06/28/2016
• Est. Priority Date: 02/12/2013
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Schlereth, Thomas, Kirsch, Markus, Gaertner, Christian, Albrecht, Tony
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US14/767,245
• Publication Number:
  US 20150372054A1
• Time in Patent Office: 874 Days
• Field of Search: 257/88
• US Class Current: 1/1
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/14 with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A semiconductor chip (10) is provided which comprises:

• • a semiconductor layer sequence (20) with a p-type semiconductor region (5) and an n-type semiconductor region (3),
  • a plurality of p-contacts (11a, 11b), which are connected electrically conductively with the p-type semiconductor region (5), and
  • a plurality of n-contacts (12a, 12b), which are connected electrically conductively with the n-type semiconductor region (3), wherein:
  • the p-contacts (11a, 11b) and the n-contacts (12a, 12b) are arranged on a rear side of the semiconductor chip (10),
  • the semiconductor chip (10) comprises a plurality of regions (21, 22) arranged adjacent one another, and
  • the regions (21, 22) each comprise one of the p-contacts (11a, 11b) and one of the n-contacts (12a, 12b).

Claims

1. An optoelectronic semiconductor chip, comprising:

a semiconductor layer sequence with a p-type semiconductor region and an n-type semiconductor region;

a plurality of p-contacts, which are connected electrically conductively with the p-type semiconductor region; and

a plurality of n-contacts, which are connected electrically conductively with the n-type semiconductor region,

wherein the p-contacts and the n-contacts are arranged on a rear side of the optoelectronic semiconductor chip,

wherein the optoelectronic semiconductor chip comprises a plurality of regions arranged adjacent one another,

wherein the regions each comprise one of the p-contacts and one of the n-contacts,

wherein a mirror layer is arranged on a side of the semiconductor layer sequence remote from a radiation exit face,

wherein a current spreading layer is arranged between the mirror layer and the n-contacts, which current spreading layer is electrically conductively connected with the n-contacts, and

wherein the current spreading layer is insulated from the mirror layer by means of a first electrically insulating layer and from the p-contacts by means of a second electrically insulating layer.

2. The optoelectronic semiconductor chip according to claim 1, wherein the plurality of regions are similar in structure.

3. The optoelectronic semiconductor chip according to claim 1, wherein the plurality of regions comprise a grid arrangement.

4. The optoelectronic semiconductor chip according to claim 1, wherein trenches are arranged between the plurality of regions, which trenches divide the semiconductor layer sequence.

5. The optoelectronic semiconductor chip according to claim 1, wherein at least two of the regions are connected in series.

6. The optoelectronic semiconductor chip according to claim 5, wherein all the regions of the semiconductor chip are connected in series.

7. The optoelectronic semiconductor chip according to claim 1, wherein at least two of the regions are connected in parallel.

8. The optoelectronic semiconductor chip according to claim 7, wherein all the regions of the optoelectronic semiconductor chip are connected in parallel.

9. The optoelectronic semiconductor chip according to claim 7, wherein the optoelectronic semiconductor chip comprises a carrier, and the at least two regions are connected in parallel by means of contact surfaces or conductor tracks arranged on the carrier.

10. The optoelectronic semiconductor chip according to claim 1, wherein the semiconductor layer sequence comprises a growth substrate, and the plurality of regions arranged adjacent one another are joined together by the growth substrate.

11. The optoelectronic semiconductor chip according to claim 1, wherein a radiation-emitting active layer is arranged between the n-type semiconductor region and the p-type semiconductor region, wherein a radiation exit face is opposite the rear side of the semiconductor chip.

12. The optoelectronic semiconductor chip according to claim 1, wherein the n-contacts are in each case electrically connected with the n-type semiconductor region by means of a plurality of through-vias, which each pass from the current spreading layer through the mirror layer and the semiconductor layer sequence.

13. The optoelectronic semiconductor chip according to claim 1, wherein the semiconductor chip is surface-mountable and the p-contacts and the n-contacts are arranged flush relative to one another.

14. The optoelectronic semiconductor chip according to claim 5, wherein the optoelectronic semiconductor chip comprises a carrier, and the at least two regions are connected in series by means of contact surfaces or conductor tracks arranged on the carrier.

15. An optoelectronic semiconductor chip, comprising:

a semiconductor layer sequence with a p-type semiconductor region and an n-type semiconductor region;

a plurality of p-contacts, which are connected electrically conductively with the p-type semiconductor region; and

a plurality of n-contacts, which are connected electrically conductively with the n-type semiconductor region,

wherein the optoelectronic semiconductor chip comprises a plurality of regions arranged adjacent one another,

wherein the regions each comprise one of the p-contacts and one of the n-contacts,

wherein a mirror layer is arranged on a side of the semiconductor layer sequence remote from a radiation exit face,

wherein a current spreading layer is arranged between the mirror layer and the n-contacts, which current spreading layer is electrically conductively connected with the n-contacts,

wherein the current spreading layer is insulated from the mirror layer by means of a first electrically insulating layer and from the p-contacts by means of a second electrically insulating layer, and

wherein the n-contacts are in each case electrically connected with the n-type semiconductor region by means of a plurality of through-vias, which each pass from the current spreading layer through the mirror layer and the semiconductor layer sequence.

16. The optoelectronic semiconductor chip according to claim 15, wherein the plurality of regions are similar in structure.

17. The optoelectronic semiconductor chip according to claim 15, wherein the plurality of regions comprise a grid arrangement.