Method for forming nanowire and semiconductor device formed with the nanowire

• US 9,379,182 B1
• Filed: 02/03/2015
• Issued: 06/28/2016
• Est. Priority Date: 02/03/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Chun Jen, Tsai, Bin-Siang, Lin, Yu Shu, Wen, Tsai-Yu, Yang, Chin-Sheng
• Primary Examiner(s): Ho, Tu-Tu
• Application Number:
  US14/612,352
• Time in Patent Office: 511 Days
• Field of Search: 257/192, 438/285
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02535 including tin
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/413 : Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for forming germanium nanowires comprises forming a semiconductor fin structure including alternating fin and shallow trench structures, etching a top portion of the fin to form a fin recess and depositing a germanium-based semiconductor into the fin recess as a germanium-based plug. The method comprises etching the shallow trench structure to expose the germanium-based semiconductor side faces. The exposed germanium-based semiconductor undergoes annealing to form high carrier mobility nanowire structures. The nanowire structures can also be formed of different diameters by selective oxidation of some of the deposited germanium-based plugs. Alternately, forming fin structures of different widths results in deposited germanium plugs of different widths to be deposited to form different thicknesses of nanowires.

Claims

1. A method for forming nanowires over a semiconductor substrate comprising:

forming a semiconductor fin structure, said fin structure including a semiconductor material formed with a plurality of fins and a shallow trench isolation formed between adjacent fins;

forming a plurality of fin recesses by removing a top portion from each of the plurality of fins so that a top surface of each of the plurality of fins lies below a top surface of the shallow trench isolation formed between adjacent fins;

forming a germanium-based semiconductor in the plurality of fin recesses as a germanium-based plug;

after forming the germanium-based semiconductor in the fin recesses, removing a top portion of the shallow trench isolation to an extent which exposes side faces of the formed germanium-based plug; and

annealing the germanium-based plug and the shallow trench isolation to form an insulator around the germanium-based plug as an insulated nanowire, and forming an insulator from at least a portion of the shallow trench isolation as an insulator layer.

2. The method of claim 1, wherein forming the semiconductor fin structure comprises forming at least one fin having a different width than a width of another one of the plurality of fins.

3. The method of claim 1, wherein after removing a top portion of the shallow trench region to expose the side faces of the formed germanium-based plug and before the annealing step, the method further comprises:

forming a mask over at least one of the germanium-based plugs and leaving at least one germanium-based plug exposed to form a partially masked semiconductor fin structure;

performing oxidization of the partially masked semiconductor fin structure; and

removing the mask from the partially masked semiconductor fin structure after the oxidation.

4. The method of claim 1, wherein the germanium-based semiconductor is selected from Ge and GeSn.

5. The method of claim 4, wherein the germanium-based semiconductor is Ge and wherein when forming the fin recesses, each fin recess has a width to height ratio of approximately 1:

1.

6. The method of claim 4, wherein the germanium-based semiconductor is GeSn and wherein when forming the fin recesses, each fin recess has a width to height ratio of approximately 1:

2.

7. The method of claim 1, further comprising a step of determining at least one first target dimension of at least one insulated nanowire prior to forming the semiconductor fin structure, and forming dimensions of the plurality fins in the semiconductor fin structure and forming the plurality of fin recesses in accordance with the at least one first target dimension of the nanowire.

8. The method of claim 7, further comprising a step of determining a second target dimension of another one of the insulated nanowire prior to forming the semiconductor fin structure, and forming dimensions of the plurality of fins in the semiconductor fin structure and forming the plurality of the fin recesses in accordance with both the first and the second target dimensions, wherein the first and second target dimensions are different from each other.