Vertically-conducting trench MOSFET

• US 9,379,187 B2
• Filed: 06/11/2015
• Issued: 06/28/2016
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kang, SooChang, Kim, YoungJae
• Primary Examiner(s): Ngo, Ngan
• Application Number:
  US14/737,060
• Publication Number:
  US 20150279939A1
• Time in Patent Office: 383 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device and a fabricating method thereof are provided. The semiconductor device include: a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width; a gate disposed in the trench; an interlayer insulating layer pattern disposed above the gate in the trench; a source region disposed within the substrate and contacting a sidewall of the upper trench part; a body region disposed below the source region in the substrate; and a contact trench disposed above the body to region and filled with a conductive material.

Claims

1. A semiconductor device comprising:

a trench disposed within an epitaxial layer of a substrate, the trench having an upper trench part that is wider than a lower trench part in width;

a gate insulating layer disposed on an inner surface of the trench;

a gate disposed within the trench;

an interlayer insulating layer pattern disposed on the gate insulating layer within the trench that includes the gate;

a source region disposed within the substrate and contacting a sidewall of the upper trench part of the trench;

a body region disposed within the epitaxial layer of the substrate;

a contact trench filled with a metal, the contact trench allowing the source region and the body region to contact each other; and

an impurity region disposed beneath the contact trench, the impurity region having the same type of impurity as the body region and having a higher concentration of impurity than the body region.

2. The device of claim 1, wherein a lower surface of the source region is formed lower than a lower surface of the contact trench.

3. The device of claim 1, wherein an upper surface of the gate is flush with or higher than the lower surface of the contact trench.

4. The device of claim 1, wherein a depth from an upper surface of the substrate to a lower surface of the contact trench is a half of a depth from the upper surface of the substrate to a lower surface of the lower trench part.

5. The device of claim 1, wherein an upper surface of the gate is flush with or lower than a lower surface of the contact trench.

6. The device of claim 1, wherein the interlayer insulating layer pattern comprises a BPSG film, HLD oxide or a combination thereof.

7. A semiconductor device comprising:

a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width;

a gate disposed in the trench;

an interlayer insulating layer pattern disposed above the gate in the trench;

a source region disposed within the substrate and contacting a sidewall of the upper trench part;

a body region disposed below the source region in the substrate; and

a contact trench disposed above the body region and filled with a conductive material.

8. The semiconductor device of claim 7, further comprising:

an impurity region disposed between the contact trench and the body region, the impurity region having the same type of impurity as the body region and having a higher concentration of impurity than the body region.

9. The semiconductor device of claim 7, wherein a portion of the source region is disposed above an upper surface of the gate.