Power device for delivering power to electronic devices and methods of assembling same

• US 9,379,618 B2
• Filed: 09/16/2014
• Issued: 06/28/2016
• Est. Priority Date: 02/08/2013
• Status: Active Grant

• Current Assignee: Smart Prong Technologies, Inc.
• Original Assignee: Advanced Charging Technologies LLC
• Inventors: Freeman, Michael H., Weaver, W. J. Jim Jr., Freeman, Mitchael C., Dieter, Robert, Santee, Brian
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): AHMED, YUSEF A
• Application Number:
  US14/487,639
• Publication Number:
  US 20150155789A1
• Time in Patent Office: 651 Days
• Field of Search: 363/16, 363/17, 363/20, 363/21.01, 363/21.02, 363/21.03, 363/62
• US Class Current: 1/1
• CPC Class Codes: H01R 31/065 with built-in electric apparatus
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/10 Arrangements incorporating converting means for enabling loads to be operated at will from different kinds of power supplies, e.g. from ac or dc
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/335 using semiconductor devices only
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 3/337 in push-pull configuration H02M3/33576 takes precedence; with self-oscillating arrangements H02M3/3382, H02M3/3385
• CPC Class Codes: H02M 3/3374 with preregulator, e.g. current injected push-pull
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An energy efficient apparatus includes a switching device, a frequency dependent reactive device, and a control element is provided. The switching device is coupled to a source of electrical power and includes a pair of transistors and is adapted to receive a control signal and to produce an alternating current power signal. The frequency of the alternating current power signal is responsive to the control signal. The frequency dependent reactive device is electrically coupled to the pair of transistors for receiving the alternating current power signal and producing an output power signal. The frequency dependent reactive device is chosen to achieve a desired voltage of the output power signal relative to the frequency of the alternating current power signal. The control element senses an actual voltage of the direct current power signal and modifies the control signal delivered to achieve the desired voltage of the direct current power signal.

Claims

1. A voltage reduction apparatus, comprising:

a switched capacitor voltage reduction circuit electrically coupled to a power source for receiving an input direct current (DC) power signal having an input voltage level from the power source and discharging an output DC power signal to an electrical device, the output DC power signal having an output voltage level that is less than the input voltage level, the switched capacitor voltage reduction circuit including a plurality of switched capacitor devices, each of the switched capacitor devices including an input switch, a capacitor and a pair of output switches;

wherein each input switch of each of the switched capacitor devices is configured to couple each capacitor of each of the switched capacitor devices in series with the power source for transmitting the input DC power signal to each capacitor;

wherein each pair of output switches of each of the switched capacitor devices is configured to couple each capacitor of each of the switched capacitor devices in parallel to discharge the output DC power signal from each of the capacitors; and

wherein the switched capacitor voltage reduction circuit is operable between a charging state and a discharging state, the charging state including each input switch operated to couple the capacitors in series with the power source to transmit the input DC power signal to charge the capacitors and each pair of output switches operated to isolate the capacitors from the electrical device, the discharging state including each input switch operated to isolate the capacitors from the power source and each pair of output switches operated to couple the capacitors in parallel to discharge the output DC power signal from the capacitors to the electrical device;

a controller including a processor configured to sense the input voltage level and transmit control signals to the switched capacitor devices for regulating each of the switched capacitor devices as a function of the sensed input voltage level; and

a vampire load elimination subsystem including a current sensor for sensing a current level of the output DC power signal, the controller configured to shut-off input power to the switched capacitor voltage reduction circuit if the sensed current level is different from a predefined current level.

2. The apparatus in accordance with claim 1, wherein the controller is configured to regulate each of the switched capacitor devices as a function of the sensed current level of the output DC power signal.

3. The apparatus in accordance with claim 2, the processor programmed to regulate the switched capacitor voltage reduction circuit to discharge the output DC power signal having a current level within a predefined range of current levels.

4. The apparatus in accordance with claim 1, wherein the controller is configured to operate to detect a current draw after a predefined period of time after input power has been shut-off to the switched capacitor voltage reduction circuit.

5. The apparatus in accordance with claim 1, further comprising a communications controller coupled to the processor for transmitting control signals to the processor to enable remote operation of the switched capacitor voltage reduction circuit.

6. The apparatus in accordance with claim 1, the charging state including a corresponding input switch in an on-position and a corresponding pair of output switches in an off-position, the discharging state including the corresponding input switch in the off-position and the corresponding pair of output switches in the on-position.

7. The apparatus in accordance with claim 6, the processor programmed to regulate each of the switched capacitor devices from the charging state to a hold state, and from the hold state to the discharging state, the hold state including the corresponding input switch and the corresponding pair of output switches in the off-position to isolate the corresponding capacitor from the power source.

8. The apparatus in accordance with claim 1, each of the input switches and the output switches including a field-effect transistor (FET) including a gate, each gate of each input FET being connected together for receiving a control signal from the processor, and each gate of each output FET being connected together for receiving another control signal from the processor.

9. The apparatus in accordance with claim 1, the plurality of switched capacitor devices including a first switched capacitor device and a second switched capacitor device, the first switched capacitor device including a first capacitor and a first input switch coupled between the first capacitor and the power source, the second switched capacitor device including a second capacitor and a second input switch coupled between the first capacitor and the second capacitor.

10. The apparatus in accordance with claim 1, further comprising a semiconductor chip, the switched capacitor voltage reduction circuit being formed on the semiconductor chip, the semiconductor chip including a substrate material including at least one of low Ohmic silicon, polysilicon, gallium nitride, gallium arsenide, silicon germanium, silicon carbide and indium phosphide.

11. The apparatus in accordance with claim 1, further comprising a buck converter electrically coupled to the power source for receiving the input DC power signal and discharging a second output DC power signal having an output voltage level that is less than the input voltage level.

12. The apparatus in accordance with claim 1, further comprising a transformer coupled to the switched capacitor voltage reduction circuit for receiving the output DC power signal from the switched capacitor voltage reduction circuit and transmitting a modified output DC power signal having a voltage level that is less than the voltage level of the output DC power signal.

13. The apparatus in accordance with claim 1, further comprising a rectifier circuit coupled between the power source and the switched capacitor voltage reduction circuit for receiving an alternative current (AC) power signal from the power source and transmitting the input DC power signal to the switched capacitor voltage reduction circuit.

14. A voltage reduction apparatus, comprising:

a switched capacitor voltage reduction circuit electrically coupled to a power source for receiving an input DC power signal having an input voltage level from the power source and discharging an output DC power signal having an output voltage level that is less than the input voltage level to an electrical device, the switched capacitor voltage reduction circuit including a plurality of switched capacitor devices, each of the switched capacitor devices including an input switch, a capacitor, and a pair of output switches;

wherein each input switch of each of the switched capacitor devices is configured to couple each capacitor of each of the switched capacitor devices in series with the power source for transmitting the input DC power signal to each capacitor;

wherein each pair of output switches of each of the switched capacitor devices is configured to couple each capacitor of each of the switched capacitor devices in parallel to discharge the output DC power signal from each of the capacitors; and

wherein the switched capacitor voltage reduction circuit is operable between a charging state and a discharging state, the charging state including each input switch operated to couple the capacitors in series with the power source to transmit the input DC power signal to charge the capacitors and each pair of output switches operated to isolate the capacitors from the electrical device, the discharging state including each input switch operated to isolate the capacitors from the power source and each pair of output switches operated to couple the capacitors in parallel to discharge the output DC power signal from the capacitors to the electrical device;

a processor programmed to sense the input voltage level and transmit control signals to the switched capacitor devices for regulating each of the switched capacitor devices as a function of the sensed input voltage level; and

a vampire load elimination subsystem including a current sensor for sensing a current level of the output DC power signal, the processor programmed to shut-off input power to the switched capacitor voltage reduction circuit if the sensed current level is different from a predefined current level and to operate to detect a current draw after a predefined period of time after input power has been shut-off to the switched capacitor voltage reduction circuit.

15. The apparatus in accordance with claim 14, the charging state including a corresponding input switch in an on-position and a corresponding pair of output switches in an off-position, the discharging state including the corresponding input switch in the off-position and the corresponding pair of output switches in the on-position, the processor programmed to regulate each of the switched capacitor devices from the charging state to a hold state, and from the hold state to the discharging state, the hold state including the corresponding input switch and the corresponding pair of output switches in the off-position to isolate the corresponding capacitor from the power source.

16. The apparatus in accordance with claim 14, each of the input switches and the output switches including a FET including a gate, each gate of each input FET being connected together for receiving a control signal from the processor, and each gate of each output FET being connected together for receiving another control signal from the processor.

17. The apparatus in accordance with claim 14, the plurality of switched capacitor devices including a first switched capacitor device and a second switched capacitor device, the first switched capacitor device including a first capacitor and a first input switch coupled between the first capacitor and the power source, the second switched capacitor device including a second capacitor and a second input switch coupled between the first capacitor and the second capacitor.

18. The apparatus in accordance with claim 14, further comprising a semiconductor chip, the switched capacitor voltage reduction circuit being formed on the semiconductor chip, the semiconductor chip including a substrate material including at least one of low Ohmic silicon, polysilicon, gallium nitride, gallium arsenide, silicon germanium, silicon carbide and indium phosphide.

19. The apparatus in accordance with claim 14, further comprising a buck converter electrically coupled to the power source for receiving the input DC power signal and discharging a second output DC power signal having an output voltage level that is less than the input voltage level.

20. The apparatus in accordance with claim 14, further comprising a transformer coupled to the switched capacitor voltage reduction circuit for receiving the output DC power signal from the switched capacitor voltage reduction circuit and transmitting a modified output DC power signal having a voltage level that is less than the voltage level of the output DC power signal.

21. The apparatus in accordance with claim 14, further comprising a rectifier circuit coupled between the power source and the switched capacitor voltage reduction circuit for receiving an AC power signal from the power source and transmitting the input DC power signal to the switched capacitor voltage reduction circuit.

22. A method of assembling a voltage reduction apparatus, including the steps of:

providing a semiconductor chip;

forming a switched capacitor voltage reduction circuit on the semiconductor chip, the switched capacitor voltage reduction circuit configured to receive an input DC power signal having an input voltage level from a power source and discharge an output DC power signal having an output voltage level that is less than the input voltage level to an electrical device, the switched capacitor voltage reduction circuit including a plurality of switched capacitor devices, each of the switched capacitor devices including a capacitor, an input switch, and a pair of output switches, each input switch of each of the switched capacitor devices is configured to couple each capacitor of each of the switched capacitor devices in series with the power source for transmitting the input DC power signal to each capacitor, each pair of output switches of each of the switched capacitor devices is configured to couple each capacitor of each of the switched capacitor devices in parallel to discharge the output DC power signal from each of the capacitors, the switched capacitor voltage reduction circuit being operable between a charging state and a discharging state, the charging state including each input switch operated to couple the capacitors in series to transmit the input DC power signal to charge the capacitors and each pair of output switches operated to isolate the capacitors from the electrical device, the discharging state including the each input switch operated to isolate the capacitors from the power source and each pair of output switches operated to couple the capacitors in parallel to discharge the output DC power signal from the capacitors to the electrical device;

coupling a controller to the switched capacitor voltage reduction circuit, the controller configured to sense the input voltage level and transmit control signals to the switched capacitor devices for regulating each of the switched capacitor devices as a function of the sensed input voltage level; and

coupling a vampire load elimination subsystem to the switched capacitor voltage reduction circuit, the vampire load elimination subsystem including a current sensor for sensing a current level of the output DC power signal, the controller configured to shut-off input power to the switched capacitor voltage reduction circuit if the sensed current level is different from a predefined current level.

23. A The method in accordance with claim 22, including the step of:

forming a rectifier circuit on the semiconductor chip, the rectifier circuit electrically coupled between the power source and the switched capacitor voltage reduction circuit for receiving an AC power signal from the power source and transmitting the input DC power signal to the switched capacitor voltage reduction circuit.