Pipelined systolic finite impulse response filter

• US 9,379,687 B1
• Filed: 02/28/2014
• Issued: 06/28/2016
• Est. Priority Date: 01/14/2014
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Mauer, Volker, Langhammer, Martin
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US14/193,477
• Time in Patent Office: 851 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H03H 17/0248 Filters characterised by a particular frequency response or filtering method
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 2220/04 Pipelined
• CPC Class Codes: H03H 2220/06 Systolic

Abstract

A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.

Claims

1. A systolic FIR filter circuit comprising:

a plurality of multipliers, each respective one of said multipliers having a respective coefficient input, a respective sample input, and a respective multiplier output;

a plurality of sample pre-adders, each respective one of said sample pre-adders connected to a sample input of a respective one of said multipliers;

an output cascade adder chain comprising a respective output adder connected to a respective multiplier output of each respective one of said multipliers, each respective output adder having a first input receiving said respective multiplier output, and, except for a first output adder in said output cascade adder chain, having a second input receiving an output of a previous one of said output adders, said output cascade adder chain further comprising a selectable number of output delays between adjacent ones of said output adders; and

an input sample chain having a first leg and a second leg;

wherein;

each respective one of said sample pre-adders receives a respective input from a respective sample point in said first leg and a respective input from a respective sample point said second leg;

said input sample chain has, between adjacent sample points in at least one of said legs, a selectable number of sample delays related to said selectable number of output delays; and

connections of inputs from said input sample chain to said sample pre-adders are adjusted to account for said selectable number.

2. The systolic FIR filter circuit of claim 1 wherein said connections are adjusted by varying patterns of wiring from said input sample chain to said sample pre-adders.

3. The systolic FIR filter circuit of claim 1 wherein said connections are adjusted by varying delays in at least one of said legs.

4. The systolic FIR filter circuit of claim 3 wherein:

said delays comprise memories; and

said delays are varied by adjusting read addresses relative to write addresses.

5. The systolic FIR filter circuit of claim 4 wherein:

said systolic FIR filter circuit is a multichannel filter circuit having a number of channels; and

each of said memories has a depth equal to said number of channels.

6. The systolic FIR filter circuit of claim 3 wherein samples are input at a common point of said first leg and said second leg.

7. The systolic FIR filter circuit of claim 1 wherein samples are input at one end of said first leg.

8. A programmable integrated circuit device configured as a systolic FIR filter circuit, said configured programmable integrated circuit device comprising:

a plurality of multipliers, each respective one of said multipliers having a respective coefficient input, a respective sample input, and a respective multiplier output;

a plurality of sample pre-adders, each respective one of said sample pre-adders connected to a sample input of a respective one of said multipliers;

an output cascade adder chain comprising a respective output adder connected to the respective multiplier output of each respective one of said multipliers, each respective output adder having a first input receiving said respective multiplier output, and, except for a first output adder in said output cascade adder chain, having a second input receiving an output of a previous one of said output adders, said an output cascade adder chain further comprising a selectable number of output delays between adjacent ones of said output adders; and

an input sample chain having a first leg and a second leg;

wherein;

each respective one of said sample pre-adders receives a respective input from a respective sample point in said first leg and a respective input from a respective sample point in said second leg;

said input sample chain has, between adjacent sample points in at least one of said legs, a selectable number of sample delays related to said selectable number of output delays;

said sample delays are implemented by on-board memories of said programmable integrated circuit device; and

said selectable number of sample delays are adjusted relative to said selectable number of output delays to maintain timing in said systolic FIR filter circuit.

9. The configured programmable integrated circuit device of claim 8 wherein said selectable number of sample delays are adjusted relative to said selectable number of output delays by adjusting read addresses relative to write addresses.

10. The configured programmable integrated circuit device of claim 8 wherein samples are input at a common point of said first leg and said second leg.

11. The configured programmable integrated circuit device of claim 8 wherein:

said systolic FIR filter circuit is a multichannel filter circuit having a number of channels; and

each of said memories has a depth equal to said number of channels.

12. The configured programmable integrated circuit device of claim 8 wherein at least one of (a) said plurality of multipliers, (b) said plurality of pre-adders, and (c) said output cascade adder chain, is implemented in one or more specialized processing blocks on said programmable integrated circuit device.

13. The configured programmable integrated circuit device of claim 12 wherein:

said number of sample delays between adjacent sample points of said second leg is one more than said number of output delays; and

said number of sample delays between adjacent sample points of said first leg is one less than said number of output delays.

14. The configured programmable integrated circuit device of claim 13 wherein:

said number of output delays is 1;

said number of sample delays between adjacent sample points of said second leg is 2; and

said first leg is a conductor.

15. The configured programmable integrated circuit device of claim 14 wherein said conductor is outside said one or more specialized processing blocks.

16. A method of configuring a programmable integrated circuit device as a systolic FIR filter circuit, said method comprising:

configuring a plurality of multipliers with, each respective one of said multipliers having a respective coefficient input, a respective sample input, and a respective multiplier output;

configuring a plurality of sample pre-adders, by connecting each respective one of said sample pre-adders to a sample input of a respective one of said multipliers;

configuring an output cascade adder chain by connecting a respective output adder to the respective multiplier output of each respective one of said multipliers, each respective output adder having a first input receiving said respective multiplier output, and, except for a first output adder in said output cascade adder chain, having a second input receiving an output of a previous one of said output adders, and further configuring a selectable number of output delays between adjacent ones of said output adders; and

configuring an input sample chain having a first leg and a second leg;

wherein;

each respective one of said sample pre-adders receives a respective input from a respective sample point in said first leg and a respective input from a respective sample point in said second leg; and

said input sample chain has, between adjacent sample points in at least one of said legs, a selectable number of sample delays related to said selectable number of output delays;

said method further comprising;

implementing said sample delays using on-board memories of said programmable integrated circuit device; and

adjusting said selectable number of sample delays relative to said selectable number of output delays to maintain timing in said systolic FIR filter circuit.

17. The method of claim 16 wherein adjusting comprises adjusting read addresses relative to write addresses.

18. The method of claim 16 further comprising configuring a sample input at a common point of said first leg and said second leg.

19. The method of claim 16 wherein:

said systolic FIR filter circuit is a multichannel filter circuit having a number of channels;

said method further comprising;

configuring each of said memories to have a depth equal to said number of channels.

20. The method of claim 16 comprising implementing at least one of (a) said plurality of multipliers, (b) said plurality of pre-adders, and (c) said output cascade adder chain, in one or more specialized processing blocks on said programmable integrated circuit device.

21. The method of claim 20 further comprising:

implementing said number of sample delays between adjacent sample points of said second leg as one more than said number of output delays; and

implementing said number of sample delays between adjacent sample points of said first leg as one less than said number of output delays.

22. The method of claim 21 wherein:

said number of output delays is 1;

said method further comprising;

implementing said number of sample delays between adjacent sample points of said second leg as 2; and

implementing said first leg as a conductor.

23. The method of claim 22 wherein said conductor is outside said one or more specialized processing blocks.

24. A systolic FIR filter circuit comprising:

an input sample chain having a first leg and a second leg; and

a plurality of taps, wherein for each of said taps, a sample from a respective sample point in said first leg is combined with a sample from a respective sample point in said second leg;

wherein;

said input sample chain has an input at a point common to both said legs; and

for each of said taps, said respective sample point in said first leg and said respective sample point in said second leg are separated from said common point by an identical number of sample points.

25. The systolic FIR filter circuit of claim 24 wherein said first leg and said second leg extend parallel to one another.

26. The systolic FIR filter circuit of claim 24 wherein:

outputs of said taps are combined in an output cascade adder chain comprising a respective adder for each of said taps and a selectable number of output delays between each of said adders; and

said input sample chain has, between adjacent sample points, a selectable number of sample delays related to said selectable number of output delays.

27. The systolic FIR filter circuit of claim 26 wherein:

said number of sample delays between adjacent sample points of said second leg is one more than said number of output delays; and

said number of sample delays between adjacent sample points of said first leg is one less than said number of output delays.

28. The systolic FIR filter circuit of claim 27 wherein:

said number of output delays is 1;

said number of sample delays between adjacent sample points of said second leg is 2; and

said first leg is a conductor.