Devices and methods for data recovery of control channels in wireless communications

• US 9,379,739 B2
• Filed: 01/07/2015
• Issued: 06/28/2016
• Est. Priority Date: 08/11/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chen, Chulong, Chincholi, Amith Vikram, Venkatachari, Harish
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US14/591,473
• Publication Number:
  US 20160043829A1
• Time in Patent Office: 538 Days
• US Class Current: 1/1
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/17 Burst error correction, e.g. error trapping, Fire codes
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

Aspects of the present disclosure provide an apparatus and methods for recovering data from a control channel in wireless communications. An apparatus decodes a CRC appended codeword to obtain a decoded codeword, and computes a first syndrome of the decoded codeword utilizing a parity check matrix. If the first syndrome is non-zero, The apparatus determines a location S and a length K of an error pattern in bits of the decoded codeword, an index set ε based on the values of S and K. A linear system is formed based on the parity check matrix and the error pattern in accordance with the index set ε. The apparatus determines a solution of the linear system, wherein the solution includes an estimated error pattern. A recovered codeword can be determined by removing the estimated error pattern from the decoded codeword.

Claims

1. A method of recovering a codeword in wireless communications, comprising:

receiving a cyclic redundancy check (CRC) appended codeword from a wireless channel;

decoding the CRC appended codeword to obtain the decoded codeword;

computing a first syndrome of the decoded codeword utilizing a parity check matrix;

if the first syndrome is non-zero, determining a location S and a length K of an error pattern in bits of the decoded codeword;

determining an index set ε

based on the values of S and K;

forming a linear system based on the parity check matrix and the error pattern in accordance with the index set ε

;

determining a solution of the linear system, wherein the solution comprises an estimated error pattern; and

determining a recovered codeword by removing the estimated error pattern from the decoded codeword.

2. The method of claim 1, wherein the wireless channel comprises a high-speed shared control channel (HS-SCCH).

3. The method of claim 1, wherein the forming the linear system comprises:

determining a sub-matrix of the parity check matrix based on the index set;

determining a sub-vector of the error pattern based on the index set; and

forming the linear system as a product of the sub-matrix and the sub-vector.

4. The method of claim 1, wherein the index set ε

is defined as;

5. The method of claim 4, wherein if the error pattern comprises information bits and excludes cyclic redundancy check (CRC) bits, setting the length K to be less than or equal to 16.

6. The method of claim 4, wherein if the error pattern comprises information bits and cyclic redundancy check (CRC) bits, setting the length K to be less than or equal to 12.

7. The method of claim 1, further comprising:

if the error pattern comprises information bits and cyclic redundancy check (CRC) bits, computing a second syndrome of the recovered codeword utilizing the parity check matrix; and

if the second syndrome is all-zero, determining that the solution of the linear system is valid.

8. An apparatus configured to recover a codeword in wireless communications, comprising:

a codeword decoder configured to receive a cyclic redundancy check (CRC) appended codeword from a wireless channel and decode the CRC appended codeword to obtain the decoded codeword;

a syndrome calculation block configured to compute a first syndrome of the decoded codeword utilizing a parity check matrix;

an error pattern location block configured to if the first syndrome is non-zero, determine a location S and a length K of an error pattern in bits of the decoded codeword;

an index set determination block configured to determine an index set ε

based on the values of S and K;

a linear system block configured to;

form a linear system based on the parity check matrix and the error pattern in accordance with the index set ε

;

determine a solution of the linear system, wherein the solution comprises an estimated error pattern; and

determine a recovered codeword by removing the estimated error pattern from the decoded codeword.

9. The apparatus of claim 8, wherein the wireless channel comprises a high-speed shared control channel (HS-SCCH).

10. The apparatus of claim 8, wherein the linear system block is further configured to:

determine a sub-matrix of the parity check matrix based on the index set;

determine a sub-vector of the error pattern based on the index set; and

form the linear system as a product of the sub-matrix and the sub-vector.

11. The apparatus of claim 8, wherein the index set ε

is defined as;

12. The apparatus of claim 11, wherein the error pattern location block is further configured to if the error pattern comprises information bits and excludes cyclic redundancy check (CRC) bits, set the length K to be less than or equal to 16.

13. The apparatus of claim 11, wherein the error pattern location block is further configured to if the error pattern comprises information bits and cyclic redundancy check (CRC) bits, set the length K to be less than or equal to 12.

14. The apparatus of claim 8, wherein the syndrome calculation block is further configured to:

if the error pattern comprises information bits and cyclic redundancy check (CRC) bits, compute a second syndrome of the recovered codeword utilizing the parity check matrix; and

if the second syndrome is all-zero, determine that the solution of the linear system is valid.

15. An apparatus configured to recover a codeword in wireless communications, comprising:

means for receiving a cyclic redundancy check (CRC) appended codeword from a wireless channel;

means for decoding the CRC appended codeword to obtain the decoded codeword;

means for computing a first syndrome of the decoded codeword utilizing a parity check matrix;

means for if the first syndrome is non-zero, determining a location S and a length K of an error pattern in bits of the decoded codeword;

means for determining an index set ε

based on the values of S and K;

means for forming a linear system based on the parity check matrix and the error pattern in accordance with the index set ε

;

means for determining a solution of the linear system, wherein the solution comprises an estimated error pattern; and

means for determining a recovered codeword by removing the estimated error pattern from the decoded codeword.

16. The apparatus of claim 15, wherein the wireless channel comprises a high-speed shared control channel (HS-SCCH).

17. The apparatus of claim 15, wherein the means for forming the linear system is configured to:

determine a sub-matrix of the parity check matrix based on the index set;

determine a sub-vector of the error pattern based on the index set; and

form the linear system as a product of the sub-matrix and the sub-vector.

18. The apparatus of claim 15, wherein the index set ε

is defined as;

19. The apparatus of claim 18, wherein the means for determining the location S and the length K is configured to if the error pattern comprises information bits and excludes cyclic redundancy check (CRC) bits, set the length K to be less than or equal to 16.

20. The apparatus of claim 18, wherein the means for determining the location S and the length K is configured to if the error pattern comprises information bits and cyclic redundancy check (CRC) bits, set the length K to be less than or equal to 12.

21. The apparatus of claim 15, wherein the means for computing the first syndrome is further configured to:

if the error pattern comprises information bits and cyclic redundancy check (CRC) bits, compute a second syndrome of the recovered codeword utilizing the parity check matrix; and

if the second syndrome is all-zero, determine that the solution of the linear system is valid.

22. A non-transitory computer-readable medium comprising instructions for recovering a codeword in wireless communications, the instructions cause an apparatus to:

receive a cyclic redundancy check (CRC) appended codeword from a wireless channel;

decode the CRC appended codeword to obtain the decoded codeword;

compute a first syndrome of the decoded codeword utilizing a parity check matrix;

if the first syndrome is non-zero, determine a location S and a length K of an error pattern in bits of the decoded codeword;

determine an index set ε

based on the values of S and K;

form a linear system based on the parity check matrix and the error pattern in accordance with the index set ε

;

determine a solution of the linear system, wherein the solution comprises an estimated error pattern; and

determine a recovered codeword by removing the estimated error pattern from the decoded codeword.

23. The computer-readable medium of claim 22, wherein the wireless channel comprises a high-speed shared control channel (HS-SCCH).

24. The computer-readable medium of claim 22, wherein for forming the linear system, the instructions further cause the apparatus to:

determine a sub-matrix of the parity check matrix based on the index set;

determine a sub-vector of the error pattern based on the index set; and

form the linear system as a product of the sub-matrix and the sub-vector.

25. The computer-readable medium of claim 22, wherein the index set ε

is defined as;

26. The computer-readable medium of claim 25, wherein for determining the location S and the length K, the instructions further cause the apparatus to if the error pattern comprises information bits and excludes cyclic redundancy check (CRC) bits, set the length K to be less than or equal to 16.

27. The computer-readable medium of claim 25, wherein for determining the location S and the length K, the instructions further cause the apparatus to if the error pattern comprises information bits and cyclic redundancy check (CRC) bits, set the length K to be less than or equal to 12.

28. The computer-readable medium of claim 22, wherein for computing the first syndrome, the instructions further cause the apparatus to:

if the error pattern comprises information bits and cyclic redundancy check (CRC) bits, compute a second syndrome of the recovered codeword utilizing the parity check matrix; and

if the second syndrome is all-zero, determine that the solution of the linear system is valid.