Transceivers with configurable integrated circuit

• US 9,379,816 B2
• Filed: 09/28/2011
• Issued: 06/28/2016
• Est. Priority Date: 09/28/2011
• Status: Active Grant

• Current Assignee: Gigamon Incorporated (Elliott Capital Advisors LP)
• Original Assignee: Gigamon Incorporated (Elliott Capital Advisors LP)
• Inventors: Yang, Yunfa
• Primary Examiner(s): Leung, Danny
• Application Number:
  US13/247,662
• Publication Number:
  US 20130077968A1
• Time in Patent Office: 1,735 Days
• Field of Search: 398135-214
• US Class Current: 1/1
• CPC Class Codes: H04B 10/40 Transceivers

Abstract

A transceiver includes a housing, an optical interface for detachably coupling to an optical transmission device, an optical-electrical conversion unit coupled to the optical interface, the optical-electrical conversion unit located in the housing, a programmable logic device communicatively coupled to the optical-electrical conversion unit, and an electrical interface communicatively coupled to the programmable logic device, wherein the electrical interface is configured for detachably coupling to an electrical transmission device. In some embodiments, the programmable logic device may be configured to perform packet filtering, packet slicing, time stamping, packet analysis, port labeling, packet masking, packet modification, packet stripping, packet de-duplication, or a combination thereof.

Claims

1. A transceiver, comprising:

an optical interface for detachably coupling to an optical transmission device;

an optical-electrical conversion unit coupled to the optical interface;

a programmable logic device communicatively coupled to the optical-electrical conversion unit, the programmable logic device including programmable logic; and

an electrical interface communicatively coupled to the programmable logic device, wherein the electrical interface is configured for detachably coupling to a network switch appliance via an electrical transmission device;

wherein the programmable logic device is configured to;

receive user-specified program instructions; and

reconfigure the programmable logic to perform packet processing according to the user-specified program instructions;

wherein packet processing includes;

packet filtering, packet slicing, time stamping, port labeling, packet masking, packet modification, packet stripping, packet de-duplication, or a combination thereof.

2. The transceiver of claim 1, further comprising:

a diagnostic unit configured to detect a predetermined condition; and

a port coupled to the diagnostic unit for reporting a detection of the predetermined condition.

3. The transceiver of claim 1, further comprising a first end and a second end, wherein the optical interface and the electrical interface are located at the first end, and the programmable logic device is located at the second end.

4. The transceiver of claim 1, wherein the programmable logic device comprises a clock recovery unit configured to determine time data for time stamping packets received at the transceiver.

5. The transceiver of claim 1, wherein the programmable logic device comprises a memory for storing information associated with a processing of packets received at the transceiver.

6. The transceiver of claim 1, further comprising a local clock unit for providing a reference clock signal.

7. The transceiver of claim 1, further comprising a power management unit coupled to the programmable logic device, wherein the power management is configured to deactivate the transceiver in response to a detected condition.

8. The transceiver of claim 1, further comprising a configuration port for configuring the programmable logic device.

9. The transceiver of claim 1, further comprising an input coupled to the programmable logic device for receiving a clock signal from an external clock.

10. The transceiver of claim 1, wherein the programmable logic device comprises a FPGA.

11. The transceiver of claim 1, wherein the programmable logic device comprises a CPLD or an EPLD.

12. A transceiver, comprising:

an optical interface for detachably coupling to an optical transmission device;

an optical-electrical conversion unit coupled to the optical interface;

a configurable processor communicatively coupled to the optical-electrical conversion unit, the configurable processor including programmable logic; and

an electrical interface communicatively coupled to the configurable processor, wherein the electrical interface is configured for detachably coupling to an electrical transmission device;

wherein the configurable processor is configured to;

receive program instructions; and

reconfigure the programmable logic to perform packet processing according to the program instructions;

wherein packet processing includes;

packet filtering, packet slicing, time stamping, port labeling, packet masking, packet modification, packet stripping, packet de-duplication, or a combination thereof.

13. The transceiver of claim 12, further comprising:

a diagnostic unit configured to detect a predetermined condition; and

a port coupled to the diagnostic unit for reporting a detection of the predetermined condition.

14. The transceiver of claim 12, further comprising a first end and a second end, wherein the optical interface and the electrical interface are located at the first end, and the configurable processor is located at the second end.

15. The transceiver of claim 12, wherein the configurable processor comprises a clock recovery unit configured to determine time data for time stamping packets received at the transceiver.

16. The transceiver of claim 12, wherein the configurable processor comprises a memory for storing information associated with a processing of packets received at the transceiver.

17. The transceiver of claim 12, further comprising a local clock unit for providing a reference clock signal.

18. The transceiver of claim 12, further comprising a power management unit coupled to the configurable processor, wherein the power management is configured to deactivate the transceiver in response to a detected condition.

19. The transceiver of claim 12, further comprising a configuration port for configuring the configurable processor.

20. The transceiver of claim 12, further comprising an input coupled to the configurable processor for receiving a clock signal from an external clock.

21. The transceiver of claim 12, wherein the configurable processor comprises a FPGA.

22. The transceiver of claim 12, wherein the configurable processor comprises a programmable logic device.