Sample rate converter and method of converting sample rate

• US 9,379,886 B2
• Filed: 07/07/2015
• Issued: 06/28/2016
• Est. Priority Date: 09/19/2014
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kim, Sang-Kyun, Park, Mi-Jeong, Eo, Ik-Soo
• Primary Examiner(s): PHU, PHUONG M
• Application Number:
  US14/793,645
• Publication Number:
  US 20160087787A1
• Time in Patent Office: 357 Days
• Field of Search: 375/355, 375/372, 375/373, 341/60, 341/61
• US Class Current: 1/1
• CPC Class Codes: H03H 17/028 Polynomial filters
• CPC Class Codes: H03H 17/0628 the input and output signals being derived from two separate clocks, i.e. asynchronous sample rate conversion
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A sample rate converter and a method of converting a sample rate are disclosed herein. The sample rate converter includes a data delay unit, a clock rate conversion unit, a Lagrange polynomial filter unit, a resample position calculation unit, and a resample position compensation unit. The data delay unit delays signals in response to an input clock signal. The clock rate conversion unit converts the sample rate of the signals. The Lagrange polynomial filter unit performs a filtering function on the signals whose rate has been converted. The resample position calculation unit outputs the value (Dint, dfrac) of the resample position of the signals based on a set resample ratio value. The resample position compensation unit corrects the error value of the signals by applying the value (Dint, dfrac) to the signals, and outputs a final signal.

Claims

1. A sample rate converter, comprising:

a data delay unit configured to delay signals in response to an input clock signal;

a clock rate conversion unit comprising a memory, the clock rate conversion unit configured to convert a sample rate of the signals;

a Lagrange polynomial filter unit configured to perform, using a Lagrange polynomial, a filtering function on the signals whose rate has been converted;

a resample position calculation unit configured to output a value of a resample position of the signals based on a set resample ratio value, the value of the resample position comprising an integer value and a factional value; and

a resample position compensation unit configured to;

correct an error value of the signals generated due to non-integer multiple sample rate conversion by applying the value of the resample position to the signals; and

output a final signal;

wherein converting the sample rate of the signals includes (i) storing the signals in the memory, and (ii) sampling, using the integer value of the value of the resample position as a memory address of the memory, the signals stored in the memory, and

wherein the resample position compensation unit includes a resample ratio error estimation unit configured to determine that an error is present in a received resample ratio when a first change point generated according to the integer value of the value of the resample position is not equal to a second change point generated according to the input clock and an output clock.

2. The sample rate converter of claim 1, wherein the clock rate conversion unit sequentially stores the input signals, sampled at an input clock rate, in the memory.

3. The sample rate converter of claim 1, wherein:

an order of a filter of the Lagrange polynomial filter unit is variably applied depending on a resample rate and a bandwidth; and

a coefficient of the filter is determined by the order.

4. The sample rate converter of claim 1, wherein a delay order of the data delay unit is determined by an order of a filter of the Lagrange polynomial filter unit, and the signals are delayed by 1 sample in response to the input clock.

5. The sample rate converter of claim 1, wherein the resample position calculation unit outputs the value of the resample position used to estimate the resample position based on the value of the resample ratio indicative of a ratio of the input clock to an output clock.

6. A sample rate converter comprising:

a data delay unit configured to delay signals in response to an input clock signal;

a clock rate conversion unit configured to convert a sample rate of the signals;

a Lagrange polynomial filter unit configured to perform, using a Lagrange polynomial, a filtering function on the signals whose rate has been converted;

a resample position calculation unit configured to output a value of a resample position of the signals based on a set resample ratio value; and

a resample position compensation unit configured to;

correct an error value of the signals generated due to non-integer multiple sample rate conversion by applying the value of the resample position to the signals; and

output a final signal;

wherein the value of the resample position comprises an integer value and a factional value,

wherein the resample position calculation unit outputs the value of the resample position used to estimate the resample position based on the value of the resample ratio indicative of a ratio of the input clock to an output clock, and

wherein the resample position calculation unit comprises;

a resample ratio error compensation unit configured to;

estimate an error between a received resample ratio and an actual operation clock ratio;

update the resample ratio value; and

compensate for a cumulative error corresponding to the updated resample ratio value; and

a resample rate calculation unit configured to;

receive a value estimated by the resample ratio error compensation unit; and

output the value of the resample position in accordance with an output sample rate.

7. The sample rate converter of claim 6, wherein the resample ratio error compensation unit comprises:

a resample ratio error estimation unit configured to estimate the error between the received resample ratio and the actual operation clock ratio; and

a computation error compensation unit configured to correct the cumulative error value that is generated due to a previous resample ratio value as the resample ratio value is updated.

8. The sample rate converter of claim 7, wherein if a change point of data generated due to the integer value of the value of the resample position is not equal to a change point of data generated between actual clocks, the resample ratio error estimation unit determines that an error is present in a received resample ratio, and updates a value of a factional ratio part of the resample ratio.

9. The sample rate converter of claim 7, wherein the resample ratio error estimation unit comprises:

a clock count block configured to output a signal, counted using the input clock, as a counted output clock signal;

computation and pulse generation blocks configured to;

determine a first difference of a first value of the counted output clock signal corresponding to a current clock cycle and a second value of the counted output clock signal corresponding to a previous clock cycle;

generate a first pulse according to whether the first difference is equal to a redetermined value set in accordance with the resample ratio;

determine a second difference of respective integer values of a first value of the resample position corresponding to the current clock cycle and a second value of a resample position corresponding to the previous clock cycle; and

generate a second pulse according to whether the second difference is equal to the predetermined value set in accordance with the resample ratio;

first and second pulse count blocks configured to calculate a pulse occurrence interval of the first and second pulses, respectively;

a comparison block configured to;

compare the first pulse with the second pulse, using the first and second pulses and the outputs of the first and second pulse count blocks; and

determine an operating rate of the integer value of the received value of the resample position; and

an update block configured to;

receive an operating state of the integer value of the value of the resample position; and

output a value FracRate_comp obtained by updating the resample ratio value with a correction unit value Comp_Fdelay.

10. The sample rate converter of claim 9, wherein the computation error compensation unit comprises:

a counter unit configured to output a count value of a section, calculated using a previous ratio, whenever the value FracRate_comp obtained by updating the resample ratio value with the correction unit value Comp_Fdelay is updated; and

an accumulation unit configured to calculate an error compensation value of the section, calculated using the previous ratio, using the value, output by the counter unit, and the correction unit value Comp_Fdelay.

11. A method of converting a sample rate, comprising:

sequentially storing input signals, sampled at an input clock rate, in a memory of a clock rate conversion unit;

outputting, by a resample position calculation unit, a value of a resample position of the signals based on a set resample ratio value, the value of the resample position comprising an integer value and a fractional value;

sampling, by the clock rate conversion unit, the signals stored in the memory, the sampling being performed at an output clock rate and using an integer value of the resample position as an address of the memory; and

correcting, by a resample position compensation unit, an error value of the signals attributable to non-integer multiple sample rate conversion by applying the value of the resample position to the signals,

wherein correcting, by the resample position compensation unit, the error value of the signal attributable to the non-integer multiple sample rate conversion by applying the value of the resample position to the signal comprises minimizing an influence of a phase offset generated between asynchronous clocks by predicting a location of the memory in which the signals to be sampled are stored and a resample position of the signal through calculation of a cumulative value of a received resample ratio.

12. The method of claim 11, wherein the value of the resample position comprises the integer value corresponding to an integer part and a factional value corresponding to a fractional part.

13. The method of claim 11, wherein sampling, by the clock rate conversion unit, the signals stored in the corresponding memory at the output clock rate by using the integer value of the resample position as the address of the corresponding memory comprises:

sequentially storing, by the clock rate conversion unit, the input signals, sampled at the input clock rate, in the memory; and

sampling the signals, stored in the corresponding memory, at the output clock rate by using an integer value of the resample position calculated by the resample position calculation unit as the address of the corresponding memory address.