Charge balancing converter using a passive integrator circuit

• US 9,383,395 B1
• Filed: 04/25/2014
• Issued: 07/05/2016
• Est. Priority Date: 04/26/2013
• Status: Active Grant

• Current Assignee: Parade Technologies, Ltd.
• Original Assignee: Parade Technologies, Ltd.
• Inventors: Ogirko, Roman, Maharyta, Andriy, Kremin, Viktor, Klein, Hans, Bihday, Volodymyr, Karpin, Oleksandr
• Primary Examiner(s): Valone, Thomas F
• Application Number:
  US14/262,614
• Time in Patent Office: 802 Days
• Field of Search: 324/679
• US Class Current: 1/1
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G06F 3/04162 for exchanging data with external devices, e.g. smart pens, via the digitiser sensing hardware
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/041662 using alternate mutual and self-capacitive scanning
• CPC Class Codes: G06F 3/0442 using active external devices, e.g. active pens, for transmitting changes in electrical potential to be received by the digitiser
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A method, apparatus, and system are described to perform, by a capacitance-sensing circuit, capacitance sensing of an electrode of a capacitive sense array of electrodes. Performing the capacitance sensing includes integrating, on a passive integrator circuit, charge from a sensed capacitance of the electrode of the capacitive sense array. The passive integrator circuit integrates the charge on a self-capacitance of the electrode as part of the integrating. The capacitance-sensing circuit converts the charge from the sensed capacitance of the electrode into a digital value representing the sensed capacitance of the electrode.

Claims

1. A method comprising:

at a capacitance-sensing circuit electrically coupled to a capacitive sense array of electrodes and including a current generator;

performing capacitance sensing of an electrode of the capacitive sense array of electrodes, including;

configuring a passive integrator circuit to include a first capacitor associated with a self-capacitance of the electrode, wherein the first capacitor is formed between the electrode and a ground;

balancing by the current generator charge integrated on the passive integrator circuit; and

sensing the charge integrated on the passive integrator circuit, wherein the sensed charge is indicative of a sensed capacitance associated with at least one of the self-capacitance and a mutual capacitance of the electrode; and

converting the sensed charge indicative of the sensed capacitance of the electrode into a digital value, wherein the digital value corresponds to a length of time for balancing the charge integrated on the passive integrator circuit and associated with the sensed capacitance of the electrode.

2. The method of claim 1, further comprising

accumulating quantization error, by an error correction circuit of the capacitance-sensing circuit, from the conversion of the charge indicative of the sensed capacitance of the electrode into the digital value.

3. The method of claim 2, wherein the accumulating of quantization error further comprises

accumulating quantization error over successive conversion cycles and converting the accumulated quantization error into the digital value, wherein a conversion cycle comprises one cycle of integrating charge indicative of the sensed capacitance.

4. The method of claim 2, wherein accumulating quantization error further comprises:

sampling the quantization error of a current conversion at the error correction circuit; and

storing the quantization error from the current conversion at the error correction circuit, wherein the quantization error of the current conversion is added to the quantization error from a previous conversion.

5. The method of claim 4, wherein the sampling and storing of the quantization error is performed by a first sample-hold capacitor and a second sample-hold capacitor of the error correction circuit.

6. The method of claim 2, wherein accumulating quantization error further comprises

selectively coupling one of a first sample-hold capacitor or a second sample-hold capacitor to an input of a differential amplifier while coupling the other one of the first sample-hold capacitor or the second sample-hold capacitor to an output of the differential amplifier, wherein the error correction circuit comprises the first sample-hold capacitor, the second sample-hold capacitor, and the differential amplifier.

7. The method of claim 2, wherein accumulating quantization error further comprises

selectively coupling one of a first sample-hold capacitor or a second sample-hold capacitor to an input of a buffer while coupling the other one of the first sample-hold capacitor or the second sample-hold capacitor to an output of the buffer, wherein the error correction circuit comprises the first sample-hold capacitor, the second sample-hold capacitor, and the buffer.

8. The method of claim 2, further comprising

varying a bias voltage of the error correction circuit when the capacitance-sensing circuit measures the electrode of the capacitive sense array in self-capacitance measuring mode.

9. The method of claim 8, wherein the bias voltage is coupled to the error correction circuit and a transmission (TX) input of the capacitive sense array.

10. The method of claim 2, wherein accumulating quantization error further comprises

selectively coupling one of a first sample-hold capacitor or a second sample-hold capacitor in a feedback configuration between an input and an output of a differential amplifier while coupling the other one of the first sample-hold capacitor or the second sample-hold capacitor to the output of the differential amplifier, wherein the error correction circuit comprises the first sample-hold capacitor, the second sample-hold capacitor, and the differential amplifier.

11. The method of claim 2, wherein accumulating quantization error further comprises

selectively coupling one of a first sample-hold capacitor or a second sample-hold capacitor to an input of a buffer while coupling the other one of the first sample-hold capacitor or the second sample-hold capacitor to an output of a differential amplifier, wherein an output of the buffer is coupled to an input of the differential amplifier, wherein the error correction circuit comprises the first sample-hold capacitor, the second sample-hold capacitor, the buffer, and the differential amplifier.

12. The method of claim 1, wherein the capacitance-sensing circuit performs capacitance sensing of the electrode of the capacitive sense array in a mutual capacitance sensing mode.

13. The method of claim 1, wherein the performing the capacitance sensing further comprises:

comparing, by a comparator of the capacitance-sensing circuit, an output voltage of an error correction circuit to a reference voltage, the comparator to produce a comparator output based on the comparison, wherein the comparator is coupled to the passive integrator circuit;

balancing the charge, by the current generator, integrated on the passive integrator circuit, wherein the current generator performs one of at least sinking or sourcing charge to the passive integrator circuit; and

controlling, by a control unit coupled to the comparator and the current generator, the current generator based on a transmission (TX) signal sent by the control unit to a TX input and on at least one of the comparator output of the comparison, a blanking signal, an end of a conversion, or a stop signal.

14. The method of claim 1, wherein balancing the charge integrated on the passive integrator circuit further comprises

applying, by the current generator, a bipolar current to the passive integrator circuit for a duration less than a half-period of a transmission (TX) signal, wherein the TX signal is an periodic waveform.

15. The method of claim 1, wherein the passive integrator circuit is external to the capacitance-sensing circuit.

16. The method of claim 1, wherein the self-capacitance of the electrode comprises parasitic capacitance from an electrode plate of the electrode to an output terminal of the electrode.

17. An apparatus comprising

a capacitance-sensing circuit electrically coupled to capacitive sense array of electrodes and including a current generator, wherein the capacitance-sensing circuit is configured to:

perform capacitance sensing of an electrode of the capacitive sense array of electrodes, including;

configuring a passive integrator circuit to include a first capacitor associated with a self-capacitance of the electrode, wherein the first capacitor is formed between the electrode and a ground;

balancing by the current generator charge integrated on the passive integrator circuit; and

sensing the charge, integrated on the passive integrator circuit, wherein the sensed charge is indicative of a sensed capacitance associated with at least one of the self-capacitance and a mutual capacitance of the electrode; and

convert the sensed charge indicative of the sensed capacitance of the electrode into a digital value, wherein the digital value corresponds to a length of time for balancing the charge integrated on the passive integrator circuit and associated with the sensed capacitance of the electrode.

18. The apparatus of claim 17, wherein the capacitance-sensing circuit further comprises

an error correction circuit to accumulate quantization error from the conversion of the charge indicative of the sensed capacitance of the electrode into the digital value, wherein the error correction circuit is to accumulate quantization error over successive conversion cycles, a conversion cycle comprises one cycle of integrating charge from a sensed capacitance and converting the charge into the digital value.

19. A system comprising:

a capacitive sense array, the capacitive sense array comprising a plurality of electrodes, wherein a first capacitor is formed between an electrode of the plurality of electrodes and a ground, associated with a self-capacitance of the electrode, and configured to become part of a passive integrator circuit, and wherein the passive integrator circuit is used to integrate charge indicative of a sensed capacitance associated with at least one of the self-capacitance and a mutual capacitance of the electrode; and

a capacitance-sensing circuit coupled to the capacitive sense array and including a current generator, wherein the capacitance-sensing circuit is configured to;

balance by the current generator the charge integrated on the passive integrator circuit,

sense the integrated charge on the passive integrator circuit, and

convert the integrated charge into a digital value, wherein the digital value corresponds to a length of time for balancing the charge integrated on the passive integrator circuit and associated with the sensed capacitance of the electrode.

20. The system of claim 19, wherein the capacitance-sensing circuit comprises an error correction circuit to accumulate quantization error from the conversion of the charge into the digital value.