Processor bridging in heterogeneous computer system

• US 9,383,811 B2
• Filed: 11/21/2011
• Issued: 07/05/2016
• Est. Priority Date: 06/08/2011
• Status: Active Grant

• Current Assignee: Institute For Information Industry
• Original Assignee: Institute For Information Industry
• Inventors: Chang, Teng-Chang
• Primary Examiner(s): Vo, Tim T
• Assistant Examiner(s): Huynh, Kim T.
• Application Number:
  US13/301,358
• Publication Number:
  US 20120317321A1
• Time in Patent Office: 1,688 Days
• Field of Search: 710305-306, 710/100, 710316-317, 718/100, 713300-340
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.

Claims

1. In a heterogeneous computer system for executing software having at least one performance processor, an x86 chipset supporting said at least one performance processor for executing tasks of said software and a hypervisor processor consuming less power than said at least one performance processor, said x86 chipset comprising a north bridge, a bridge logic device comprising:

a hypervisor operation logic maintaining status of said system under said at least one performance processor;

a processor language translator logic translating between processor languages of said at least one performance and said hypervisor processors; and

a high-speed bus switch having first, second and third ports for relaying data across any two of said three ports bidirectionally, wherein said first port is connected to said at least one performance processor via a first front-side bus, said second port is connected to said hypervisor processor via said processor language translator logic and a second front-side bus, and said third port is connected to said north bridge of said x86 chipset via a third front-side bus, wherein said at least one performance processor and said hypervisor processor all access said north bridge via said third front-side bus.

2. The bridge logic device of claim 1 wherein said hypervisor processor, supported by said x86 chipset and with said high-speed bus switch connecting across said second and third ports, executes tasks of said software said hypervisor processor has sufficient processing power to handle by using native language translated by said processor language translator logic and putting said at least one performance processor to a power-conserving state.

3. The bridge logic device of claim 1 wherein said hypervisor processor, using said maintained system status and with said high-speed bus switch connecting across said first and third ports, brings up said at least one performance processor out of said power-conserving state to execute tasks of said software said hypervisor processor has insufficient processing power to handle.

4. The bridge logic device of claim 1 wherein said at least one performance and hypervisor processors, with said high-speed bus switch connecting across said first, second and third ports correspondingly, simultaneously execute tasks of said software that require combined processing power of all processors.

5. The bridge logic device of claim 1 wherein said processor language translator logic further comprising:

a peripheral interrupt request controller controlling interrupt requests by peripheral devices attached to said heterogeneous computer system;

a peripheral status table keeping the status of said peripheral devices; and

a peripheral status maintainer updating said status kept in said peripheral status table based on the control by said peripheral interrupt request controller.

6. The bridge logic device of claim 1 wherein said hypervisor operation logic further comprising:

a front-side bus command handler monitoring computer commands performed by said at least one performance processor for maintaining said system status; and

a bus wrapper translating between languages of said at least one performance and hypervisor processors to allow for direct access by said hypervisor processor to said x86 chipset for executing tasks of said software.

7. The bridge logic device of claim 1 wherein each of said at least one performance processor and said hypervisor processor are x86 processors and are on the same semiconductor chip.

8. The bridge logic device of claim 1 wherein each of said at least one performance processor is an x86 processor, said hypervisor processor is an ARM processor and all are on the same semiconductor chip.

9. The bridge logic device of claim 1 wherein said bridge logic device is on an independent semiconductor chip.

10. The bridge logic device of claim 1 wherein said bridge logic device is on the same semiconductor chip as that of said hypervisor processor.

11. The bridge logic device of claim 1 wherein said bridge logic device, said hypervisor processor and said at least one performance processor are on the same semiconductor chip.