Speculative finish of instruction execution in a processor core
First Claim
1. A processor core, comprising:
- a data structure including multiple entries for tracking high latency operations associated with instructions executed by the processor core;
an execution pipeline that executes instructions, wherein the execution pipeline, prior to completion of a high latency operation tracked by an entry of the data structure, speculatively finishes execution of an instruction dependent on the high latency operation by reporting an identifier of the entry and freeing a resource in the execution pipeline utilized by the instruction; and
completion logic that, responsive to the identifier of the entry, records a dependence of the instruction on the high latency operation and commits an execution result of the instruction to an architected state of the processor core only after successful completion of the high latency operation, wherein the completion logic, in response to unsuccessful completion of the high latency operation, flushes the instruction without committing the execution result to the architected state and causes the processor core to reissue the instruction with an indication that speculative finishing of the instruction is inhibited.
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Abstract
In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.
51 Citations
8 Claims
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1. A processor core, comprising:
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a data structure including multiple entries for tracking high latency operations associated with instructions executed by the processor core; an execution pipeline that executes instructions, wherein the execution pipeline, prior to completion of a high latency operation tracked by an entry of the data structure, speculatively finishes execution of an instruction dependent on the high latency operation by reporting an identifier of the entry and freeing a resource in the execution pipeline utilized by the instruction; and completion logic that, responsive to the identifier of the entry, records a dependence of the instruction on the high latency operation and commits an execution result of the instruction to an architected state of the processor core only after successful completion of the high latency operation, wherein the completion logic, in response to unsuccessful completion of the high latency operation, flushes the instruction without committing the execution result to the architected state and causes the processor core to reissue the instruction with an indication that speculative finishing of the instruction is inhibited. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification