×

Speculative finish of instruction execution in a processor core

  • US 9,384,002 B2
  • Filed: 11/16/2012
  • Issued: 07/05/2016
  • Est. Priority Date: 11/16/2012
  • Status: Expired due to Fees
First Claim
Patent Images

1. A processor core, comprising:

  • a data structure including multiple entries for tracking high latency operations associated with instructions executed by the processor core;

    an execution pipeline that executes instructions, wherein the execution pipeline, prior to completion of a high latency operation tracked by an entry of the data structure, speculatively finishes execution of an instruction dependent on the high latency operation by reporting an identifier of the entry and freeing a resource in the execution pipeline utilized by the instruction; and

    completion logic that, responsive to the identifier of the entry, records a dependence of the instruction on the high latency operation and commits an execution result of the instruction to an architected state of the processor core only after successful completion of the high latency operation, wherein the completion logic, in response to unsuccessful completion of the high latency operation, flushes the instruction without committing the execution result to the architected state and causes the processor core to reissue the instruction with an indication that speculative finishing of the instruction is inhibited.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×