Flash memory architecture with separate storage of overhead and user data

• US 9,384,127 B2
• Filed: 11/20/2013
• Issued: 07/05/2016
• Est. Priority Date: 08/25/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Estakhri, Petro, Nemazie, Siamack
• Primary Examiner(s): Tran, Denise
• Application Number:
  US14/084,777
• Publication Number:
  US 20140082271A1
• Time in Patent Office: 958 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A dedicated overhead block of the plurality of dedicated overhead blocks has a plurality of overhead segments. The overhead segments have physical block address registers configured to store physical block addresses defining respective dedicated data blocks.

Claims

1. A memory device, comprising:

a plurality of dedicated data blocks for storing user data, wherein each of the plurality of dedicated data blocks is at a respective location in the memory device that is identified by a respective single physical block address; and

a plurality of dedicated overhead blocks for storing overhead data, wherein each of the plurality of dedicated overhead blocks is at a respective location in the memory device that is identified by a respective single physical block address;

wherein a dedicated overhead block of the plurality of dedicated overhead blocks comprises a plurality of overhead segments, wherein each of the plurality of overhead segments comprises a physical block address register configured to store the respective single physical block address that identifies the respective location in the memory device of a data block of the plurality of dedicated data blocks.

2. The memory device of claim 1, wherein an overhead segment of the plurality of overhead segments supports an amount of user data stored in a single dedicated data block of the plurality of dedicated data blocks.

3. The memory device of claim 1, wherein an overhead segment of the plurality of overhead segments is configured to define a status of user data and a status of a dedicated data block of the plurality of dedicated data blocks whose respective location in the memory device is identified by the respective single physical address stored in the physical block address register in that overhead segment.

4. The memory device of claim 1, further comprising a space manager that is configured to address only the overhead data.

5. The memory device of claim 1, wherein different overhead segments of the plurality of overhead segments are to store overhead data for user data corresponding to different logical block addresses.

6. A memory device, comprising:

a plurality of dedicated data blocks for storing user data, wherein each of the plurality of dedicated data blocks is at a respective location in the memory device that is identified by a respective single physical block address; and

a plurality of dedicated overhead blocks for storing overhead data, wherein each of the plurality of dedicated overhead blocks is at a respective location in the memory device that is identified by a respective single physical block address;

wherein each dedicated overhead block comprises a plurality of overhead segments, wherein different overhead segments of the plurality of overhead segments are to store overhead data for user data corresponding to different logical block addresses; and

wherein each overhead segment of the plurality of overhead segments comprises a physical block address register that cross references overhead data to user data.

7. A memory device, comprising:

a plurality of dedicated data blocks for storing user data, wherein each of the plurality of dedicated data blocks is at a respective location in the memory device that is identified by a respective single physical block address; and

a plurality of dedicated overhead blocks for storing overhead data, wherein each of the plurality of dedicated overhead blocks is at a respective location in the memory device that is identified by a respective single physical block address;

wherein each dedicated overhead block comprises a first overhead data field comprising a plurality of first overhead segments and a second overhead data field comprising a plurality of second overhead segments; and

wherein each of the plurality of first overhead segments is pre-assigned to a different specific virtual logical block address and wherein the second overhead segments of the plurality of second overhead segments are not pre-assigned to specific virtual logical block addresses.

8. A memory device, comprising:

a plurality of dedicated data blocks for storing user data, wherein each of the plurality of dedicated data blocks is at a respective location in the memory device that is identified by a respective single physical block address; and

a plurality of dedicated overhead blocks for storing overhead data, wherein each of the plurality of dedicated overhead blocks is at a respective location in the memory device that is identified by a respective single physical block address;

wherein each dedicated overhead block comprises a first overhead field comprising a plurality of pages of overhead segments and a second overhead field comprising a plurality of pages of overhead segments;

wherein each page of the plurality of pages of overhead segments in the first overhead field comprises an extension region to store a status of the overhead segments in that page; and

wherein each of the overhead segments in the first overhead field is pre-assigned to a different specific virtual logical block address.

9. A memory device, comprising:

a plurality of dedicated data blocks for storing user data, wherein each of the plurality of dedicated data blocks is at a respective location in the memory device that is identified by a respective single physical block address; and

a plurality of dedicated overhead blocks for storing overhead data, wherein each of the plurality of dedicated overhead blocks is at a respective location in the memory device that is identified by a respective single physical block address;

wherein each dedicated overhead block of the plurality of dedicated overhead blocks comprises a first overhead data field comprising a plurality of overhead segments and a second overhead data field comprising a plurality of pages of second overhead segments;

wherein a first second overhead segment of each page of the plurality of pages of second overhead segments comprises a status segment that comprises an update map; and

wherein each of the plurality of first overhead segments is pre-assigned to a different virtual logical block address.

10. The memory device of claim 9, wherein the second overhead segments are not preassigned to specific virtual logical block addresses.

11. The memory device of claim 9, wherein each update map comprises a number of registers equal to a number of first overhead segments of the plurality of first overhead segments.

12. The memory device of claim 9, wherein each update map in a respective dedicated overhead block of the plurality of dedicated overhead blocks gives a location within the respective dedicated overhead block of each current overhead segment within the respective dedicated overhead block regardless of whether the current overhead segment is a first or a second overhead segment.

13. A memory device, comprising:

a plurality of dedicated data blocks for storing user data; and

a plurality of dedicated overhead blocks for storing overhead data;

wherein a dedicated overhead block of the plurality of dedicated overhead blocks comprises a first overhead field and a second overhead field, the first and second overhead fields comprising a plurality of consecutively addressable overhead pages;

wherein consecutively addressable segments of the consecutively addressable overhead pages within the first overhead field of a dedicated overhead block are respectively correlated to sequentially addressed virtual logical block addresses; and

wherein overhead segments within the second overhead data field are not pre-assigned to specific virtual logical block addresses.

14. The memory device of claim 13, wherein consecutively addressable segments of the consecutively addressable overhead pages within an overhead page of the second overhead field comprise a status segment.

15. A memory device, comprising:

a plurality of dedicated data blocks for storing user data; and

a plurality of dedicated overhead blocks for storing overhead data;

wherein a dedicated overhead block of the plurality of dedicated overhead blocks comprises a plurality of super overhead fields, a super overhead field comprising a whole number of pages, each super overhead field within the dedicated overhead block comprising an identical number of pages, wherein consecutive overhead segments within a page are respectively assigned to consecutively addressed virtual logical block addresses of a plurality of virtual logical blocks of user data.

16. The memory device of claim 15, wherein each overhead segment comprises a flag field, comprising a move-pending flag and a move-complete flag.

17. The memory device of claim 16, wherein the flag field further comprises a used flag, an obsolete flag, and a defective flag.

18. The memory device of claim 15, wherein each page comprises an extension field for storing a super virtual logical block address that corresponds to the dedicated overhead block.

19. The memory device of claim 18, wherein the memory device is configured to use information stored in the extension field to correlate logical and physical addresses within a space manager of the memory device on power up.

20. The memory device of claim 15, wherein an address specifier of a space manager of the memory device is configured to reference a number of a page currently in use in the dedicated overhead block.