Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques

• US 9,384,317 B1
• Filed: 03/31/2014
• Issued: 07/05/2016
• Est. Priority Date: 11/01/2013
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Pribetich, Olivier, Matsunami, Gary, Salowe, Jeffrey S., Raj, Satish, Sharma, Karun, Lee, Yinnie
• Primary Examiner(s): Alam, Mohammed
• Application Number:
  US14/231,713
• Time in Patent Office: 827 Days
• Field of Search: 716/112
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.

Claims

1. A computer implemented method for implementing physical electronic designs, comprising:

using a computing system having at least one processor or at least one processor core to perform a process, the process comprising;

identifying, with a physical implementation rule mechanism including or functioning with the at least one processor or the at least one processor core, one or more first design rules;

identifying or determining a set of tracks for a region of interest on a first layer of an electronic design based at least in part upon the one or more first design rules that govern the set of tracks and design data of a first type of circuit component designs in the electronic design;

identifying one or more second design rules; and

generating at least a portion of a physical design for the region of interest using the set of tracks and the one or more second design rules, wherein the physical design of the at least a portion is correct-by-construction with respect to the one or more first design rules.

2. The computer implemented method of claim 1, wherein the physical design of the at least a portion of the region of interest automatically satisfies the one or more first design rules, without performing any design rule checking with respect to the one or more first design rules.

3. The computer implemented method of claim 1, the process further comprising:

identifying a first portion not implemented using the set of tracks or the one or more second design rules; and

implementing the first portion with regard to the one or more second design rules.

4. The computer implemented method of claim 1, the process further comprising:

identifying a second portion from the first portion of the electronic design;

identifying one or more violations of the one or more first design rules; and

fixing at least one of the one or more violations of the one or more violations.

5. The computer implemented method of claim 1, the act of identifying or determining the set of tracks comprising:

identifying one or more boundary pins for the region of interest;

identifying one or more instances in the region of interest;

identifying one or more instance pins for at least one of the one or more instances in the region of interest; and

identifying or determining the set of tracks based at least in part upon the one or more boundary pins, the one or more instance pins, or a combination of the one or more boundary pins and the one or more instance pins.

6. The computer implemented method of claim 5, wherein the act of identifying or determining the set of tracks includes:

identifying tracks from a greater set of grid lines, wherein the tracks are aligned with a most number of the one or more boundary pins, the one or more instance pins, or a combination of the one or more boundary pins and the one or more instance pins.

7. The computer implemented method of claim 5, wherein the act of identifying or determining the set of tracks includes:

identifying a first boundary pin not intersecting or aligned with any track in the set of one or more tracks;

determining whether the first boundary pin can be moved to another location;

identifying one or more rules governing placement or routing for the first boundary pin; and

identifying a first track from the set of tracks for the first boundary pin.

8. The computer implemented method of claim 7, wherein the act of identifying or determining the set of tracks includes:

moving the first boundary pin to a new location determined based at least in part upon the first track and a boundary of the region of interest.

9. The computer implemented method of claim 7, wherein the act of identifying or determining the set of tracks includes:

maintaining the first boundary pin in an original location;

creating a new boundary segment by augmenting or offsetting at least an original boundary segment of the region of interest;

creating a new boundary pin for the first boundary pin in a new location determined based at least in part upon the new boundary and the first track; and

creating one or more interconnections electrically connecting the new boundary pin and the first boundary pin.

10. The computer implemented method of claim 7, wherein the act of identifying or determining the set of tracks includes:

maintaining the first boundary pin in an original location;

creating a new boundary pin for the first boundary pin in a new location determined based at least in part upon a boundary of the region of interest and the first track; and

creating one or more interconnections electrically connecting the new boundary pin and the first boundary pin.

11. The computer implemented method of claim 5, wherein the act of identifying or determining the set of tracks includes:

identifying a cell instance, an instance pin in the cell instance, and a boundary pin connected to the instance pin;

identifying a third design rule governing the instance pin and the boundary pin, wherein a combination of the instance pin and the boundary pin causes a violation of the third design rule; and

evaluating one or more options for resolving the violation of the third design rule.

12. The computer implemented method of claim 11, wherein the act of identifying or determining the set of tracks includes at least one of:

moving the instance pin to a new instance pin location without moving the cell instance;

moving the cell instance to a new cell instance location;

moving the boundary pin to a new boundary pin location;

inserting one or more vias for the instance pin; and

flagging the instance pin.

13. A system for implementing physical electronic designs, comprising:

a computing system having at least one processor or at least one processor core that is to;

identify, with a physical implementation rule mechanism including or functioning with the at least one processor or the at least one processor core, one or more first design rules;

identify or determine a set of tracks for a region of interest on a first layer of an electronic design based at least in part upon the one or more first design rules that govern the set of tracks and design data of a first type of circuit component designs in the electronic design;

identify one or more second design rules; and

generate at least a portion of a physical design for the region of interest using the set of tracks and the one or more second design rules, wherein the physical design of the at least a portion is correct-by-construction with respect to the one or more first design rules.

14. The system of claim 13, wherein the at least one processor or at least one processor core is further to:

identify a first portion not implemented using the set of tracks or the one or more second design rules; and

implement the first portion with regard to the one or more second design rules.

15. The system of claim 13, wherein the at least one processor or at least one processor core is further to:

identify a second portion from the first portion of the electronic design;

identify one or more violations of the one or more first design rules; and

fix at least one of the one or more violations of the one or more violations.

16. The system of claim 13, wherein the at least one processor or at least one processor core that is to identify or determine the set of tracks is further to:

identify one or more boundary pins for the region of interest;

identify one or more instances in the region of interest;

identify one or more instance pins for at least one of the one or more instances in the region of interest;

identify or determine the set of tracks based at least in part upon the one or more boundary pins, the one or more instance pins, or a combination of the one or more boundary pins and the one or more instance pins; and

identify tracks from a greater set of grid lines, wherein the tracks are aligned with a most number of the one or more boundary pins, the one or more instance pins, or a combination of the one or more boundary pins and the one or more instance pins.

17. The system of claim 16, wherein the at least one processor or at least one processor core that is to identify or determine the set of tracks is further to:

identify a first boundary pin not intersecting or aligned with any track in the set of one or more tracks;

determine whether the first boundary pin can be moved to another location;

identify one or more rules governing placement or routing for the first boundary pin; and

identify a first track from the set of tracks for the first boundary pin.

18. The system of claim 16, wherein the at least one processor or at least one processor core that is to identify or determine the set of tracks is further to:

identify a cell instance, an instance pin in the cell instance, and a boundary pin connected to the instance pin;

identify a third design rule governing the instance pin and the boundary pin, wherein a combination of the instance pin and the boundary pin causes a violation of the third design rule; and

evaluate one or more options for resolving the violation of the third design rule.

19. The system of claim 17, wherein the at least one processor or at least one processor core that is to identify or determine the set of tracks is further to:

maintain the first boundary pin in an original location;

create a new boundary segment by augmenting or offsetting at least an original boundary segment of the region of interest;

create a new boundary pin for the first boundary pin in a new location determined based at least in part upon the new boundary and the first track; and

create one or more interconnections electrically connecting the new boundary pin and the first boundary pin.

20. The system of claim 17, wherein the at least one processor or at least one processor core that is to identify or determine the set of tracks is further to:

maintain the first boundary pin in an original location;

create a new boundary pin for the first boundary pin in a new location determined based at least in part upon a boundary of the region of interest and the first track; and

create one or more interconnections electrically connecting the new boundary pin and the first boundary pin.

21. The system of claim 17, wherein the at least one processor or at least one processor core that is to identify or determine the set of tracks is further to:

identify a cell instance, an instance pin in the cell instance, and a boundary pin connected to the instance pin;

identify a third design rule governing the instance pin and the boundary pin, wherein a combination of the instance pin and the boundary pin causes a violation of the third design rule; and

evaluate one or more options for resolving the violation of the third design rule.

22. The system of claim 21, wherein the at least one processor or at least one processor core that is to identify or determine the set of tracks is further to:

move the instance pin to a new instance pin location without moving the cell instance;

move the cell instance to a new cell instance location;

move the boundary pin to a new boundary pin location;

insert one or more vias for the instance pin; and

flag the instance pin.

23. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing physical electronic designs, the set of acts comprising:

identifying, with a physical implementation rule mechanism including or functioning with the at least one processor or the at least one processor core, one or more first design rules;

identifying or determining a set of tracks for a region of interest on a first layer of an electronic design based at least in part upon the one or more first design rules that govern the set of tracks and design data of a first type of circuit component designs in the electronic design;

identifying one or more second design rules; and

generating at least a portion of a physical design for the region of interest using the set of tracks and the one or more second design rules, wherein the physical design of the at least a portion is correct-by-construction with respect to the one or more first design rules.

24. The article of manufacture of claim 23, the set of acts further comprising:

identifying a first portion not implemented using the set of tracks or the one or more second design rules; and

implementing the first portion with regard to the one or more second design rules.

25. The article of manufacture of claim 23, the set of acts further comprising:

identifying a second portion from the first portion of the electronic design;

identifying one or more violations of the one or more first design rules; and

fixing at least one of the one or more violations of the one or more violations.

26. The article of manufacture of claim 23, the act of identifying or determining the set of tracks comprising:

identifying one or more boundary pins for the region of interest;

identifying one or more instances in the region of interest;

identifying one or more instance pins for at least one of the one or more instances in the region of interest; and

identifying or determining the set of tracks based at least in part upon the one or more boundary pins, the one or more instance pins, or a combination of the one or more boundary pins and the one or more instance pins.

27. The article of manufacture of claim 26, wherein the act of identifying or determining the set of tracks includes:

identifying tracks from a greater set of grid lines, wherein the tracks are aligned with a most number of the one or more boundary pins, the one or more instance pins, or a combination of the one or more boundary pins and the one or more instance pins.

28. The article of manufacture of claim 26, wherein the act of identifying or determining the set of tracks includes:

identifying a first boundary pin not intersecting or aligned with any track in the set of one or more tracks;

determining whether the first boundary pin can be moved to another location;

identifying one or more rules governing placement or routing for the first boundary pin; and

identifying a first track from the set of tracks for the first boundary pin.

29. The article of manufacture of claim 28, wherein the act of identifying or determining the set of tracks includes:

moving the first boundary pin to a new location determined based at least in part upon the first track and a boundary of the region of interest.

30. The article of manufacture of claim 28, wherein the act of identifying or determining the set of tracks includes:

maintaining the first boundary pin in an original location;

creating a new boundary segment by augmenting or offsetting at least an original boundary segment of the region of interest;

creating a new boundary pin for the first boundary pin in a new location determined based at least in part upon the new boundary and the first track; and

creating one or more interconnections electrically connecting the new boundary pin and the first boundary pin.

31. The article of manufacture of claim 28, wherein the act of identifying or determining the set of tracks includes:

maintaining the first boundary pin in an original location;

creating a new boundary pin for the first boundary pin in a new location determined based at least in part upon a boundary of the region of interest and the first track; and

creating one or more interconnections electrically connecting the new boundary pin and the first boundary pin.

32. The article of manufacture of claim 26, wherein the act of identifying or determining the set of tracks includes:

a first set of acts, comprising;

identifying a cell instance, an instance pin in the cell instance, and a boundary pin connected to the instance pin;

identifying a third design rule governing the instance pin and the boundary pin, wherein a combination of the instance pin and the boundary pin causes a violation of the third design rule; and

evaluating one or more options for resolving the violation of the third design rule;

or

a second set of acts, comprising;

moving the instance pin to a new instance pin location without moving the cell instance;

moving the cell instance to a new cell instance location;

moving the boundary pin to a new boundary pin location;

inserting one or more vias for the instance pin; and

flagging the instance pin.