Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features

• US 9,384,822 B2
• Filed: 03/17/2014
• Issued: 07/05/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: GSI Technology Incorporated
• Original Assignee: GSI Technology Incorporated
• Inventors: Park, Soon-Kyu, Cha, Gi-Won, Shu, Lee-Lean, Chiang, Paul M.
• Primary Examiner(s): Oberly, Eric
• Application Number:
  US14/217,343
• Publication Number:
  US 20140289460A1
• Time in Patent Office: 841 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4077 Precharging or discharging
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Claims

1. A DRAM device involving data signals grouped into 10 bits, the DRAM device comprising:

a memory core;

input circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer;

memory circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output;

wherein the DRAM device stores and processes the DBI bit on an internal data bus as a regular data bit; and

a data bypass circuit including an input coupled to the memory core, a write buffer storing addresses, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the write buffer is retrieved instead of data from the memory core when the comparator determines that the address stored in the write buffer matches the read address, thereby causing the output data signal to bypass the DBI logic.

2. The device of claim 1, wherein a Din bus comprises:

a bus driver characterized by a first capacitance load, a second capacitance load and a decoupling capacitor coupled between the first capacitance load and the second capacitance load.

3. The device of claim 1, wherein a Din bus comprises:

a bus driver characterized by a first capacitance load and a second capacitance load, wherein one of the capacitance loads is high-go-low while the other capacitance load is low-go-high.

4. The device of claim 1, wherein a Din bus comprises:

a bus driver including a first capacitance load supplying a second capacitance load with charge via a decoupling capacitor.

5. The device of claim 1, wherein a Din bus comprises:

a bus driver including a discharge of a first capacitance load supplies charge to a second capacitance load through a decoupling capacitor to reduce power consumption and/or switching noise.

6. The device of claim 1, wherein the input buffer comprises a double data rate address bus that inputs a first half of an address in a first half of a clock cycle, inputs a second half of the address in a second half of the clock cycle, and outputs the entire address at the falling edge of the clock.

10. The device of claim 1 further comprising:

a plurality of sense lines connecting sense circuitry to output circuitry, wherein one or more DBI format sense lines are pre-charged high;

wherein half or more of the sense lines are amplified to a final state of high.

11. The device of claim 1 further including a plurality sense lines connecting sense circuitry to output circuitry, wherein one or more DBI format sense lines are pre-charged high.

12. The device of claim 11 wherein half or more of the sense lines are amplified to a final state of high.

13. The device of claim 1 further including a plurality sense lines connecting sense circuitry to output circuitry, wherein all DBI format sense lines are pre-charged high.

14. The device of claim 1 further comprising a read circuit configured to receive an output of a sense circuit and choose data to pass based on the output of the sense circuit.

15. The device of claim 1 wherein a power consumption of the memory array is reduced by the storage of the DBI bit into the memory array.

16. The device of claim 1, wherein the input buffer comprises a double data rate address bus that inputs a first half of an address in a first half of a clock cycle, inputs a second half of the address in a second half of the clock cycle, and outputs the entire address at the falling edge of the clock.

17. The invention of claim 1, further comprising:

a write buffer, comprising;

write address registers/latches corresponding to data input registers/latches of the input circuitry;

an address comparator to compare a read address and write addresses stored in the write buffer,

wherein the DBI formatted data and the DBI bit from the data input registers are output to data output registers when the address comparator matches the read address to the write address in the write buffer.

18. The invention of claim 17, wherein a power consumption of the memory array is reduced by the data output retrieval at the data output registers retrieved from the data input registers.

19. The invention of claim 17, wherein a speed of a memory retrieval operation is increased by the data output retrieval at the data output registers retrieved from the data input registers compared with data output retrieval through the memory core.

7. A DRAM device, including:

a data bus inversion (DBI) bus involving data signals grouped into 10 bits, the DBI bus comprising;

a data bus configured such that no more than half the data bits are set to low;

circuitry including a DBI data bit indicating whether the data bus is to be inverted;

a power supply bus shared by the data bus and the DBI data bit;

a ground bus shared by the data bus and the DBI data bit; and

a decoupling capacitor provided between the power supply bus and the ground bus;

a memory core; and

a data bypass circuit including an input coupled to the memory core, a write buffer storing addresses, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the write buffer is retrieved instead of data from the memory core when the comparator determines that the address stored in the write buffer matches the read address, thereby causing the output data signal to bypass the DBI bus.

8. The device of claim 7, further comprising:

a first capacitance load, a second capacitance load and the decoupling capacitor between the first capacitance load and second capacitance load.

9. The device of claim 8, wherein discharge of the first capacitance load supplies charge to the second capacitance load through the decoupling capacitor to perform complementary output switching.

20. A method of DRAM memory operation involving data signals grouped into 10 bits, the method comprising:

receiving a data bus inversion (DBI) bit and data bits as input;

outputting the DBI bit and the data bits to section circuitry;

writing the data bits into bit lines of a memory array;

comparing a read address to addresses stored in a write buffer;

when the read address does not match the addresses stored in the write buffer, reading the data bits from the memory array;

when the read address matches the addresses stored in the write buffer, reading data from the write buffer instead of data from the memory array, thereby causing the output data signal to bypass DBI logic; and

outputting the DBI formatted data bits and the DBI bits;

wherein data format of the data from the data input, throughout storage in the memory array and one or more write coherency registers, to the data output, is DBI format.