Semiconductor memory device, memory system including the same, and operating method thereof

• US 9,384,846 B1
• Filed: 07/07/2015
• Issued: 07/05/2016
• Est. Priority Date: 02/03/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Park, Bong Yeol, Shim, Keon Soo
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Dinh, Minh
• Application Number:
  US14/792,920
• Time in Patent Office: 364 Days
• Field of Search: 365/211
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Disclosed are a semiconductor memory device, a memory system including the same, and an operating method thereof. The memory system includes: a semiconductor memory device including a plurality of memory chips; and a controller configured to measure a cell current of each of the plurality of memory chips, generate temperature compensation data corresponding to the measured cell current, and store the generated temperature compensation data in each of the plurality of memory chips.

Claims

1. A memory system, comprising:

a semiconductor memory device including a plurality of memory chips; and

a controller configured to measure a cell current of each of the plurality of memory chips, generate temperature compensation data corresponding to the measured cell current, and store the generated temperature compensation data in each of the plurality of memory chips,

wherein the controller includes;

a cell current information receiving unit configured to receive cell current information from each of the plurality of memory chips and temporarily store the received cell current information; and

a temperature compensation quantity determining unit configured to generate the temperature compensation data corresponding to each of the plurality of memory chips based on the cell current information stored in the cell current information receiving unit.

2. The memory system of claim 1, wherein the controller reads the temperature compensation data stored in a selected memory chip, which is to perform a read operation, among the plurality of memory chips, and sets a read voltage according to the read temperature compensation data during the read operation.

3. The memory system of claim 1, wherein each of the plurality of memory chips includes a plurality of memory blocks, measures cell currents of cell strings included in selected representative memory blocks among the plurality of memory blocks during a cell current measurement operation, and outputs information on the measured cell current to the controller.

4. The memory system of claim 1, wherein the controller further includes

a read voltage setting unit configured to output a control signal for adjusting a read voltage according to the temperature compensation data.

5. The memory system of claim 4, wherein the controller further includes a temperature data receiving unit for receiving current operation temperature information from each of the plurality of memory chips, and temporarily stores the received current operation temperature information.

6. The memory system of claim 5, wherein the temperature compensation quantity determining unit corrects the temperature compensation data according to the current operation temperature information stored in the temperature data receiving unit.

7. The memory system of claim 1, wherein each of the plurality of memory chips includes:

a memory cell array including a plurality of memory blocks;

a peripheral circuit configured to store the temperature compensation data in a selected memory block among the plurality of memory blocks or read the stored temperature compensation data, and measure the cell current of the selected memory block during a cell current measurement operation; and

a control logic configured to control the peripheral circuit to store or read the temperature compensation data, and sense the measured cell current and a current operation temperature and output the sensed measured cell current and the current operation temperature to the controller, or adjust a potential level of a read voltage in response to a control signal received from the controller.

8. The memory system of claim 1, wherein when the measured cell current is increased, a threshold voltage variation amount according to a temperature is decreased, and when the measured cell current is decreased, a compensation quantity of a read voltage used during a read operation is gradually increased.

9. A semiconductor memory device, comprising:

a plurality of memory chips,

wherein each of the plurality of memory chips include;

a memory cell array including a plurality of memory blocks;

a peripheral circuit configured to measure a cell current of a selected memory block among the plurality of memory cell blocks, and store temperature compensation data in one or more of the plurality of memory cell blocks; and

a control logic configured to generate the temperature compensation data according to the measured cell current, and control the peripheral circuit to program the generated temperature compensation data in the one or more of the plurality of memory cell blocks,

wherein when the measured cell current is decreased, a threshold voltage variation amount of memory cells included in the memory cell array according to a temperature is increased.

10. The semiconductor memory device of claim 9, wherein the control logic controls the peripheral circuit to read the temperature compensation data stored in the selected memory block during a read operation.

11. The semiconductor memory device of claim 10, wherein the control logic resets a read voltage according to the read temperature compensation data and a current operation temperature.

12. The semiconductor memory device of claim 11, wherein the control logic further includes a temperature detection unit configured to sense the current operation temperature.

13. The semiconductor memory device of claim 9, wherein the control logic included in each of the plurality of memory chips sets a read voltage corresponding to each of the plurality of memory chips according to the measured cell current of each of the plurality of memory chips.

14. A method of a memory system, comprising:

measuring a cell current for each of a plurality of memory chips;

generating temperature compensation data corresponding to each of the plurality of memory chips according to the measured cell current;

storing the temperature compensation data in each of the plurality of memory chips; and

reading the temperature compensation data stored in each of the plurality of memory chips, setting a read voltage of each of the plurality of memory chips according to the read temperature compensation data, and performing the read operation,

wherein the temperature compensation data is generated so that when the cell current is decreased, a compensation quantity of the read voltage is increased.

15. The method of claim 14, wherein the measuring of the cell current includes measuring cell currents of selected memory blocks among a plurality of memory blocks included in each of the plurality of memory chips.

16. The method of claim 15, wherein the measuring of the cell current includes:

applying a bias to a common source line of the selected memory blocks, and then measuring the cell current through a page buffer electrically coupled with the selected memory blocks, or

applying the bias to bit lines electrically coupled with the selected memory blocks, and then measuring the cell current through the common source line.

17. The method of claim 14, wherein the setting of the read voltage includes setting the read voltage based on the temperature compensation data and a current operation temperature of one of the memory chips among the plurality of memory chips.

18. The method of claim 14, further comprising:

sensing a current quantity by a plurality of page buffers and outputting the sensed current quantity as cell current information.