System-on-chip having special function register and operating method thereof

• US 9,384,855 B2
• Filed: 11/11/2013
• Issued: 07/05/2016
• Est. Priority Date: 12/11/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Eun-Ji, Lee, Dong-Han, Kong, Jae-Sop, Chun, Kee-Moon
• Primary Examiner(s): Shin, Christopher
• Application Number:
  US14/076,300
• Publication Number:
  US 20140164726A1
• Time in Patent Office: 967 Days
• Field of Search: 713/600, 713/500, 713/400, 713/322, 710/58, 716/108, 714/744, 327/141
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry

Abstract

Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.

Claims

1. A system on chip (SoC) including a special function register (SFR), wherein the SFR comprising:

a first update storage element;

a second update storage element;

a first update logic corresponding to the first update storage element; and

a second update logic corresponding to the second update storage element,

wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.

2. The SoC of claim 1, wherein at a first time, the clock is supplied to the first update storage element and not supplied to the second update storage element, and at a second time which is different from the first time, the clock is not supplied to the first update storage element and supplied to the second update storage element.

3. The SoC of claim 2, wherein the first update logic and the second update logic are enabled using different enable signals.

4. The SoC of claim 1, wherein the first update logic supplies at least one clock to the first update storage element corresponding to a first signal, and the second update logic supplies the at least one clock to the second update storage element corresponding to a second signal.

5. The SoC of claim 4, wherein the first update logic updates data stored in the first update storage element according to the first signal, and the second update logic updates data stored in the second update storage element according to the second signal.

6. The SoC of claim 1, wherein the SFR further comprises:

a read access logic configured to transmit data read from the first update storage element and the second update storage element;

a write access logic configured to receive data to be written to the first update storage element and the second update storage element; and

a bus interface logic configured to interface between the read access logic and a bus or the write access logic and the bus.

7. The SoC of claim 6, wherein in response to the bus performing a read access, the clock is supplied to the read access logic and the bus interface logic,

in response to the bus performing a write access, the clock is supplied to the write access logic and the bus interface logic, and

in response to an access not performed by the bus, the clock is not supplied to the read access logic, the write access logic, and the bus interface logic.

8. The SoC of claim 7, wherein the SFR further comprises:

a bus monitor logic configured to detect an access, and

in response to the access of the bus being detected, supplying at least one clock to the bus interface logic and the read access logic or the write access logic.

9. The SoC of claim 1, wherein the SFR further comprises:

a reference logic configured to transmit the data stored in the first update storage element and the second storage element to an internal logic,

wherein the clock is not supplied to the reference logic.

10. The SoC of claim 1, wherein each of the first update storage element and the second update storage element include at least one flip-flop.

11. A system on chip (SoC) including a special function register (SFR), the SFR comprising:

an input port configured to receive a main clock;

a first update storage element configured to receive a first clock which is generated from the main clock; and

a second update storage element configured to receive a second clock generated from the main clock,

wherein in response to one of the first update storage element and the second update storage element being activated, the first clock and the second clock are different from each other.

12. The SoC of claim 11, wherein in response to one of the first update storage element and the second update storage element being activated, the first clock is at a first frequency, and the second clock is at a second frequency which is different from the first frequency.

13. The SoC of claim 11, wherein the SFR further comprises:

an update logic configured to supply at least one clock to the first update storage element and the second update storage element by gating the main clock.

14. The SoC of claim 13, wherein in response to one of the first update storage element and the second update storage element being activated, the update logic supplies the main clock to the activated update storage element of the one of the first update storage element and the second update storage element and interrupts supply of the main clock to the deactivated update storage element which is not the one of the first update storage element and the second update storage element.

15. An operating method of a system on chip (SoC) including a special function register (SFR) comprising a first update storage element, a second update storage element, and an update logic, the operating method comprising:

supplying at least one clock to the first update storage element by the update logic in a first status;

interrupting supply of the at least one clock to the first update storage element by the update logic in a second status;

supplying the at least one clock to the second update storage element by the update logic in the first status; and

interrupting supply of the at least one clock to the second update storage element by the update logic in the second status.

16. The method of claim 15, further comprising:

enabling the update logic corresponding to a first signal before the update logic supplies the at least one clock to the first update storage element; and

enabling the update logic corresponding to a second signal before the update logic supplies the at least one clock to the second update storage element.

17. The method of claim 15, further comprising:

supplying the at least one clock to the first update storage element and the second update storage element in a third status.

18. The method of claim 17, wherein the update logic supplies the at least one clock for a reference time in the third status.

19. A system on chip (SoC) including a special function register (SFR), the SoC comprising:

a special function register (SFR);

a memory configured to store data;

a processor configured to process the data using the SFR; and

a bus configured to connect the processor, the memory, and the SFR to each other,

wherein the SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, and in response to the first update logic being enabled, a clock is supplied to the first update storage element, and in response to the second update logic being enabled, the clock is supplied to the second update storage element.

20. The SoC of claim 19, wherein at a first time, the clock is supplied to the first update storage element and not supplied to the second update storage element, and at a second time which is different from the first time, the clock is not supplied to the first update storage element and supplied to the second update storage element.

21. The SoC of claim 19, wherein the first update logic supplies at least one clock to the first update storage element corresponding to a first signal, and the second update logic supplies the at least one clock to the second update storage element corresponding to a second signal.

22. The SoC of claim 19, wherein the SFR further comprises:

a read access logic configured to transmit data read from the update storage elements, a write access logic configured to receive data to be written to the update storage elements, and a bus interface logic configured to interface between the read access logic and a bus or the write access logic and the bus.

23. The SoC of claim 22, wherein in response to the bus performing a read access, the clock is supplied to the read access logic and the bus interface logic, in response to the bus performing a write access, the clock is supplied to the write access logic and the bus interface logic, and in response to an access not performed by the bus, the clock is not supplied to the read access logic, the write access logic, and the bus interface logic.

24. The SoC of claim 23, wherein the SFR further comprises:

a bus monitor logic configured to detect the access of the bus, and in response to the access of the bus being detected, supplying the at least one clock to the bus interface logic and the read access logic or the write access logic.

25. The SoC of claim 19, wherein the SFR further comprises:

a reference logic configured to transmit the data stored in the first update storage element and the second update storage element to an internal logic,

wherein the clock is not supplied to the reference logic.

26. An operating method of a special function register (SFR), the method comprising:

supplying a plurality of clocks to respective storage cells in a plurality of respective storage elements during an init time;

interrupting the supplying of the plurality of clocks to the respective storage cells after a lapse of the init time;

detecting an update signal and entering a snoop status which occurs after the lapse of the init time;

enabling a bus update logic corresponding to the update signal and entering a toggle state;

supplying a clock to a bus update storage element in the toggle status; and

interrupting the clock supply to the bus update storage element and entering the snoop status if another update signal is not detected.

27. The method of claim 26, further comprising:

detecting a sync signal in the snoop status;

enabling a sync update logic in response to the sync signal and entering the toggle status; and

supplying the clock to the sync update storage element in the toggle status.

28. The method of claim 27, further comprising:

interrupting the supply of the clock to the sync update storage element if another sync signal is not detected after a lapse of a snoop time in the snoop status.