Computer system predicting memory failure

• US 9,384,858 B2
• Filed: 11/21/2014
• Issued: 07/05/2016
• Est. Priority Date: 11/21/2014
• Status: Active Grant

• Current Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Inventors: Yazdanbakhsh, Amir, Balasubramanian, Raghuraman, Nowatzki, Anthony, Sankaralingam, Karthikeyan
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US14/549,979
• Publication Number:
  US 20160148707A1
• Time in Patent Office: 592 Days
• Field of Search: 714/719, 714/721, 714/745, 714/819, 714/824, 365/201
• US Class Current: 1/1
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/06 Acceleration testing
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

The prediction of memory failure is obtained by reducing the voltage on a bank of memory cells to momentarily artificially age the memory cells and subjecting the memory cells to a test in which one or more predetermined vectors are written to and read from the memory cells to detect memory cell errors.

Claims

1. An integrated circuit system comprising:

a plurality of memory cells organized in groups and addressable to allow reading and writing of binary values to the memory cells;

a voltage control system independently applying a controllable voltage to the memory cells of different groups;

a memory reliability circuit communicating with the memory cells and voltage control system to, for a given group;

(a) reduce the voltage applied to the given group using the voltage control system to less than an operating voltage applied to other memory cells of other groups to simulate aging of the given group;

(b) write a test vector to the memory cells of the given group;

(c) read the test vector from the memory cells of the given group as a modified test vector change by any memory cell failure;

(d) compare the test vector to the modified test vector; and

(e) provide an output indicating predicted failure of the given group when the test vector does not match the modified test vector.

2. The integrated circuit system of claim 1 wherein the memory reliability circuit cycles through the groups of memory cells changing the given group in each cycle.

3. The integrated circuit system of claim 1 further including error correction circuitry associated with each group for correcting an effect of memory cell failure up to a predetermined number of memory cell failures and wherein the memory reliability circuit reads the modified test vector from the memory cells of the group after correction of errors by the error correction circuitry.

4. The integrated circuit system of claim 3 further including decommissioning circuitry for decommissioning a group of memory cells upon receiving the output indicating predicted failure of the group.

5. The integrated circuit system of claim 4 wherein the decommissioning circuitry decommissions the group of memory upon receiving the output indicating predicted failure of the group but not upon a failure less than the predetermined number of memory cell failures detected by the error correction circuitry.

6. The integrated circuit system of claim 1 further including decommissioning circuitry for decommissioning a group of memory cells upon receiving the output indicating predicted failure of the group.

7. The integrated circuit system of claim 1 wherein memory reliability circuit further ensures preservation of the data of the group at another storage location before writing the test vector.

8. The integrated circuit system of claim 1 wherein the memory cells are a cache memory.

9. The integrated circuit system of claim 1 wherein the test vector writes a nonuniform predetermined data pattern to the memory cells of the data group to promote memory cell failures promoted by interaction of memory cells.

10. The integrated circuit system of claim 1 wherein the integrated circuit system includes a processor providing precise interrupts and wherein the memory reliability circuit uses a precise interrupt to start the series of steps (a)-(e).

11. The integrated circuit system of claim 1 wherein the voltage reduction simulates an aging of the memory cells by less than one month.

12. The integrated circuit system of claim 11 wherein the voltage reduction simulates an aging of the memory cells by less than one day.

13. The integrated circuit system of claim 1 wherein the memory reliability circuit receives a data value controlling an amount of aging.

14. The integrated circuit system of claim 1 wherein the memory cells are static random access memory cells.

15. The integrated circuit system of claim 1 wherein the integrated circuit system further includes at least a first and second redundant circuit module each including multiple logic gates subject to increased gate delay with age, the first and second redundant circuit modules generating first and second respective outputs;

and

gate reliability circuitry operating to;

(a) momentarily and selectively apply a stress to the first redundant circuit module in a manner mimicking age-increased gate delay without applying the stress to the second redundant circuit module;

(b) capture first and second values based on the respective first and second outputs from first and second redundant circuit modules during the stressing; and

(c) compare the captured first and second values to detect errors caused by the selective stressing.

16. The integrated circuit system of claim 15 wherein the gate reliability circuit executes step (a) at nonoverlapping times with execution by the memory reliability circuit of steps (a)-(c).

17. The integrated circuit system of claim 15 wherein the gate reliability circuit initiates an execution of step (a) repeatedly at a different rate than an initiation of execution by the memory reliability circuit of steps (a)-(c).

18. A method of predicting memory cell failure in an integrated circuit system having a plurality of memory cells organized in groups and addressable to allow reading and writing of binary values to the memory cells and having a voltage control system independently applying a controllable voltage to the memory cells of the different groups, the method comprising the steps of:

(a) reducing the voltage applied to the given group using the voltage control system to less than an operating voltage applied to other memory cells of other groups to simulate aging of the given group;

(b) writing a test vector to the memory cells of the given group;

(c) reading the test vector from the memory cells of the given group as a modified test vector changed by any memory cell failure;

(d) comparing the test vector to the modified test vector; and

(e) providing an output indicating predicted failure of the given group when the test vector does not match the modified test vector.