Carbon layer and method of manufacture

• US 9,384,991 B2
• Filed: 08/24/2015
• Issued: 07/05/2016
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Dal, Mark van
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US14/834,081
• Publication Number:
  US 20150364329A1
• Time in Patent Office: 316 Days
• Field of Search: 257/E21.09, 257/E21.296, 438/664
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is eptiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.

Claims

1. A method comprising:

depositing a metal on a (111) substrate, the (111) substrate comprising a carbon-containing material;

reacting the metal with the carbon-containing material by performing a first anneal on the metal and the (111) substrate to form a metal-containing compound layer and a graphene layer on the metal-containing compound layer distal from the (111) substrate;

after the reacting, transferring the graphene layer to a device substrate, graphite not being formed after the reacting and before the transferring;

forming a gate electrode proximate the graphene layer on the device substrate; and

forming a first contact and a second contact to the graphene layer on the device substrate, the first contact and the second contact being on opposite sides of the gate electrode.

2. The method of claim 1 wherein the performing the first anneal is performed at a temperature equal to or less than 200 °

C.

3. The method of claim 1, wherein the (111) substrate is a (111) silicon carbide substrate, the carbon-containing material being silicon carbide of the (111) silicon carbide substrate.

4. The method of claim 1, wherein the metal is deposited with a thickness not exceeding 10 nm.

5. The method of claim 1, wherein the graphene layer has a thickness not exceeding 5 nm.

6. The method of claim 1 further comprising after the reacting the metal with the carbon-containing material and before the transferring the graphene layer, curing the graphene layer by performing a second anneal at a temperature greater than the first anneal.

7. The method of claim 1, wherein the device substrate includes the gate electrode and a gate dielectric over the gate electrode, the graphene layer being transferred to the device substrate over the gate dielectric, the first contact and the second contact being formed over the graphene layer.

20. The method of claim 1, after reacting the metal, curing the graphene layer prior to transferring.

8. A method comprising:

forming a first dielectric layer on a first substrate;

forming a gate electrode embedded in the first dielectric layer;

forming a gate dielectric layer on the first dielectric layer and the gate electrode;

forming a graphene layer on a second substrate;

after forming the graphene layer, curing the graphene layer;

after curing the graphene layer, transferring a graphene layer onto the gate dielectric layer; and

forming a first contact and a second contact to the graphene layer, the first contact and the second contact being on opposite lateral sides of the gate electrode, the graphene layer being disposed vertically between the gate electrode and the first contact.

9. The method of claim 8 further comprising, after transferring the graphene layer, patterning the graphene layer.

10. The method of claim 8, wherein the forming the gate electrode comprises:

forming an opening in the first dielectric layer; and

depositing the gate electrode in the opening.

11. The method of claim 8, wherein forming the graphene layer comprises:

depositing a metal on a (111) substrate, the (111) substrate comprising a carbon-containing material; and

reacting the metal with the carbon-containing material by performing a first anneal on the metal and the (111) substrate to form a metal-containing compound layer and the graphene layer on the metal-containing compound layer distal from the (111) substrate.

12. The method of claim 11, wherein the reacting the metal with the carbon-containing material does not form graphite.

13. The method of claim 11 wherein the performing the first anneal is performed at a temperature equal to or less than 200 °

C.

14. The method of claim 11, wherein the (111) substrate is a (111) silicon carbide substrate, the carbon-containing material being silicon carbide of the (111) silicon carbide substrate.

15. The method of claim 11, wherein the metal is deposited with a thickness not exceeding 10 nm.

16. The method of claim 11, wherein the graphene layer has a thickness not exceeding 5 nm.

17. The method of claim 11, wherein the curing is performed by performing a second anneal at a temperature greater than the first anneal.

18. A method comprising:

depositing a metal on a (111) SiC substrate;

epitaxially growing a silicide over the (111) SiC substrate and a graphene layer over the silicide by performing a first anneal on the metal and the (111) SiC substrate, the first anneal causing the metal to react with the (111) SiC substrate to epitaxially grow the silicide and the graphene layer as products of the reaction, the reaction not forming graphite;

curing the graphene layer by performing a second anneal at a temperature greater than a temperature of the first anneal;

forming a first dielectric layer on a device substrate;

forming a gate electrode embedded in the first dielectric layer;

forming a gate dielectric layer on the first dielectric layer and the gate electrode;

transferring the graphene layer onto the gate dielectric layer; and

forming a first contact and a second contact to the graphene layer, the first contact and the second contact being on opposite lateral sides of the gate electrode, the graphene layer being disposed vertically between the gate electrode and the first contact.

19. The method of claim 18, wherein:

the metal has a thickness that does not exceed 10 nm,

the metal is nickel, platinum, cobalt, palladium, copper, iron, or a combination thereof,

the first anneal is at a temperature of 200 °

C. or less,

the graphene layer has a thickness that does not exceed 5 nm, and

the second anneal is at a temperature in a range of 500 °

C. to 1,100 °

C.