Systems and methods involving data bus inversion memory circuitry, configuration and/or operation

• US 9,385,032 B2
• Filed: 03/17/2014
• Issued: 07/05/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: GSI Technology Incorporated
• Original Assignee: GSI Technology Incorporated
• Inventors: Shu, Lee-Lean
• Primary Examiner(s): Oberly, Eric
• Application Number:
  US14/217,164
• Publication Number:
  US 20140289440A1
• Time in Patent Office: 841 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, memory devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Claims

1. A memory device comprising:

a memory core;

input circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer;

at least one memory circuit that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output, wherein the memory device stores and processes the DBI bit on an internal data bus as a regular data bit; and

a data buffering circuit coupled to the memory core, the data buffering circuit including a write buffer comprising a data register positioned between the input circuitry and the DBI logic and storing the data to be written into the memory core on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the DBI logic when the comparator determines that the address stored in the address register matches the read address, thereby causing the output data signal to bypass the DBI logic.

2. The device of claim 1, wherein the memory core is configured to store the DBI bit to reduce conversion of the data stream and associated power consumption.

3. The device of claim 1, wherein the input circuitry comprises:

a bus driver characterized by a first capacitance load, a second capacitance load and a decoupling capacitor coupled between the first capacitance load and the second capacitance load.

4. The device of claim 1, wherein the input circuitry comprises:

a bus driver characterized by a first capacitance load and a second capacitance load, wherein the maximum bus switching occurs when approximately half of the capacitance loads is high-go-low while the other half of capacitance load is low-go-high.

5. The device of claim 1, wherein the input circuitry comprises:

a bus driver including a first capacitance load supplying a second capacitance load with charge via a decoupling capacitor.

12. The device of claim 1, wherein the DBI logic accepts a data bus and the DBI bit as input.

13. The device of claim 1, wherein the DBI logic provides the DBI bit and outputs to a data bus.

14. The device of claim 1, wherein the device is configured to perform internal data bus processing of the DBI bit into the memory array to thereby reduce current consumption and current spikes.

17. The device of claim 1, wherein the memory device is configured to generate the DBI formatted internal data bus to thereby reduce power consumption associated with long global data bus loading in the write operation.

19. The device of claim 1, wherein bypassing the DBI logic reduces power consumption and noise and increases device speed.

20. The device of claim 1, wherein read circuitry coupled to the memory core is configured to perform a non-DBI read operation.

6. A memory device comprising:

a memory array;

local data writing circuitry coupled to the memory array, the local data writing circuitry comprising a local data write driver and a local data bus inversion (DBI) converter circuitry;

wherein the local DBI converter circuitry converts DBI formatted data to non-DBI formatted data; and

wherein the local data writing circuitry writes the non-DBI formatted data to the memory array;

sense circuitry coupled to the memory array to read out the non-DBI formatted data and output sense data;

a DBI formatter circuit coupled to an output of the sense circuitry to format the sense data into DBI formatted data and a DBI bit;

an output buffer coupled to an output of the DBI formatter circuit and outputting the DBI bit and DBI formatted data; and

a data buffering circuit including a write buffer comprising a data register coupled to the local DBI converter circuitry and storing non-converted data to be written into the memory array on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer,

wherein data from the data register is retrieved as an output data signal instead of data from the memory array when the comparator determines that the address stored in the address register matches the read address, thereby causing the non-converted data to bypass the local DBI converter circuitry.

7. The device of claim 6, wherein the memory device is configured to receive and process the DBI formatted data by handling DBI conversion at the local data writing circuitry to reduce current consumption and current spikes.

8. The device of claim 6, wherein the local data writing circuitry comprises:

a bus driver characterized by a first capacitance load, a second capacitance load and a decoupling capacitor coupled between the first capacitance load and the second capacitance load.

9. The device of claim 6, wherein the local data writing circuitry comprises:

a bus driver including a discharge of a first capacitance load supplies charge to a second capacitance load through a decoupling capacitor to reduce power consumption and/or switching noise.

10. The device of claim 6, wherein the local data writing circuitry comprises:

coupling circuitry connected between a power supply bus and a ground bus, wherein the coupling circuitry provides an electrical path between a first capacitance load and a second capacitance load such that charge is supplied to the coupling circuitry from the power supply bus and the first capacitance load to a decoupling capacitor for data bit switching of the first capacitance load, and then the coupling circuitry supplies the charge from the decoupling capacitor to the second capacitance load for data bit switching of the second capacitance load.

11. The device of claim 6, wherein the local data writing circuitry comprises:

coupling circuitry configured to switch data bits in a first capacitance load and provide a charge from the first capacitance load to a decoupling capacitor, and switch data bits in a second capacitance load and provide the charge of the decoupling capacitor to the second capacitance load.

15. The device of claim 6, wherein the DBI converter logic accepts the DBI formatted data bits and the DBI bit as input.

16. The device of claim 6, wherein the DBI formatter logic outputs the DBI formatted data bits and the DBI bit.

21. The device of claim 6, wherein bypassing the local DBI converter circuitry reduces power consumption and noise and increases device speed.

22. The device of claim 6, wherein read circuitry coupled to the memory array is configured to perform a non-DBI read operation.

18. A method for memory operation utilizing data bus inversion, method comprising the steps of:

receiving a data bus inversion (DBI) bit and data bits as input;

outputting the DBI bit and the data bits to section circuitry;

storing the data bits in a data register;

comparing an address stored in an address register with a read address;

when the address stored in the address register does not match the read address;

performing DBI converter logic in the section circuitry to convert the data bits;

writing the converted data bits into bit lines of a memory array;

reading the converted data bits from the memory array;

performing DBI formatter logic at an output buffer; and

outputting the DBI formatted data bits and the DBI bits; and

when the address stored in the address register matches the read address;

writing the data bits from the data register into bit lines of a memory array, thereby bypassing the DBI converter logic.

23. The method of claim 18, further comprising reading the data written to the memory array via a non-DBI read operation.