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Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same

  • US 9,385,047 B2
  • Filed: 06/23/2015
  • Issued: 07/05/2016
  • Est. Priority Date: 01/31/2012
  • Status: Active Grant
First Claim
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1. A method of producing an integrated circuit, comprising:

  • forming an epitaxial layer on a wafer;

    forming, on an unsingulated die of the wafer, a plurality of first NFETs, each having a first gate stack, and a first nominal threshold voltage;

    forming, on the unsingulated die, a plurality of first PFETs, each having a second gate stack and a second nominal threshold voltage;

    forming, on the unsingulated die, a plurality of second NFETs, each having a third gate stack, and a third nominal threshold voltage;

    forming, on the unsingulated die, a plurality of second PFETs, each having the third gate stack and a fourth nominal threshold voltage;

    wherein the plurality of second NFETs has a channel foundation layer that includes a first heavily doped screening layer below the epitaxial layer, and the plurality of second PFETs has a channel foundation layer that includes a second heavily doped screening layer below the epitaxial layer.

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