Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
First Claim
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1. A method of producing an integrated circuit, comprising:
- forming an epitaxial layer on a wafer;
forming, on an unsingulated die of the wafer, a plurality of first NFETs, each having a first gate stack, and a first nominal threshold voltage;
forming, on the unsingulated die, a plurality of first PFETs, each having a second gate stack and a second nominal threshold voltage;
forming, on the unsingulated die, a plurality of second NFETs, each having a third gate stack, and a third nominal threshold voltage;
forming, on the unsingulated die, a plurality of second PFETs, each having the third gate stack and a fourth nominal threshold voltage;
wherein the plurality of second NFETs has a channel foundation layer that includes a first heavily doped screening layer below the epitaxial layer, and the plurality of second PFETs has a channel foundation layer that includes a second heavily doped screening layer below the epitaxial layer.
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Abstract
Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.
505 Citations
14 Claims
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1. A method of producing an integrated circuit, comprising:
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forming an epitaxial layer on a wafer; forming, on an unsingulated die of the wafer, a plurality of first NFETs, each having a first gate stack, and a first nominal threshold voltage; forming, on the unsingulated die, a plurality of first PFETs, each having a second gate stack and a second nominal threshold voltage; forming, on the unsingulated die, a plurality of second NFETs, each having a third gate stack, and a third nominal threshold voltage; forming, on the unsingulated die, a plurality of second PFETs, each having the third gate stack and a fourth nominal threshold voltage; wherein the plurality of second NFETs has a channel foundation layer that includes a first heavily doped screening layer below the epitaxial layer, and the plurality of second PFETs has a channel foundation layer that includes a second heavily doped screening layer below the epitaxial layer. - View Dependent Claims (2, 3)
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4. A method of forming an integrated circuit, comprising:
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forming, in substrate, a plurality of NFET channel foundations, a plurality of PFET channel foundations, a plurality of DDC-NFET channel foundations, and a plurality DDC-PFET channel foundations; forming on the channel foundations, a blanket substantially undoped epitaxial layer; and disposing a first NFET gate stack over a first one of the plurality of NFET channel foundations, disposing a first PFET gate stack over a first one of the PFET channel foundations, disposing a first DDC-NFET gate stack over a first one of the DDC-NFET channel foundations, disposing a first DDC-PFET gate stack over a first one of the DDC-PFET channel foundations; wherein the first NFET gate stack and the first PFET gate stack are different from each other; and wherein each of the NFET, PFET, DDC-NFET and DDC-PFETs are isolated from one another using an isolation structure that is formed after the formation of the blanket substantially undoped epitaxial layer. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification