Semiconductor device and structure

• US 9,385,058 B1
• Filed: 03/14/2013
• Issued: 07/05/2016
• Est. Priority Date: 12/29/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian, Sekar, Deepak
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): Baptiste, Wilner Jean
• Application Number:
  US13/803,437
• Time in Patent Office: 1,209 Days
• Field of Search: 257/347, 257/712, 257/758
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/098 : the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An Integrated Circuit device, including: a base wafer including first electronic circuits and a plurality of first single crystal transistors; at least one metal layer; and a second layer including second electronic circuits and a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; the second layer includes a through layer via with a diameter of less than 150 nm; a portion of the first electronic circuits is circumscribed by a first dice lane, and there are no conductive connections to the portion of the first electronic circuits that cross the first dice lane; wherein a portion of the second electronic circuits is circumscribed by a second dice lane, and there are no conductive connections to the portion of the second electronic circuits that cross the second dice lane, and the second dice lane is overlaying and aligned to the first dice lane.

Claims

1. An Integrated Circuit device, comprising:

a base wafer comprising first electronic circuits, said first electronic circuits comprising a plurality of first single crystal transistors;

at least one metal layer providing interconnection between said plurality of first single crystal transistors; and

a second layer on a plane comprising second electronic circuits, said second electronic circuits comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer;

wherein said second layer comprises a through layer via with a diameter of less than 400 nm;

wherein a portion of said first electronic circuits is circumscribed by a first dice lane of at least 10 microns width, and there are no conductive connections to said portion of said first electronic circuits that cross said first dice lane;

wherein a portion of said second electronic circuits is circumscribed by a second dice lane of at least 10 microns width, and there are no conductive connections to said portion of said second electronic circuits that cross said second dice lane, and

wherein said second dice lane is overlaying and aligned to said first dice lane and a bulk body, said base wafer comprising said bulk body; and

at least one thermal conducting path from at least one of said plurality of second single crystal transistors to the bulk body.

2. The Integrated Circuit device according to claim 1, further comprising:

at least one shielding layer, said at least one shielding layer overlying said at least one metal layer;

wherein said second layer is overlying said at least one shielding layer, and

wherein said at least one shielding layer is constructed to provide at least 2 times greater heat conduction in the horizontal direction than in the vertical direction.

3. The Integrated Circuit device according to claim 1, further comprising:

at least one shielding layer, said at least one shielding layer overlying said at least one metal layer;

wherein said second layer is overlying said at least one shielding layer,

wherein said base wafer comprises a bulk body, and

wherein said at least one shielding layer is constructed to provide heat conduction to the bulk body.

4. The Integrated Circuit device according to claim 1,

wherein said second layer thickness is less than one micron.

5. The Integrated Circuit device according to claim 1,

wherein said second layer comprises at least one conductive pad for connecting power to said device,

wherein said conductive pad is aligned to said plurality of first single crystal transistors with less than 200 nm alignment error.

6. The Integrated Circuit device according to claim 1, further comprising:

a first electrically conductive grid underneath said second layer, said first electrically conductive grid is constructed to provide power to at least one of said plurality of first transistors; and

a second electrically conductive grid overlaying said second single crystal transistors, said second electrically conductive grid is constructed to provide power to at least one of said plurality of second single crystal transistors;

wherein said second electrically conductive grid has a substantially higher current conduction capacity than said first electrically conductive grid.

7. An Integrated Circuit device, comprising:

a base wafer comprising a plurality of first single crystal transistors;

at least one metal layer providing interconnection between said plurality of first single crystal transistors;

at least one shielding layer overlying said at least one metal layer; and

a second layer of less than 2 micron thickness, said second layer on a plane and comprising a plurality of second single crystal transistors, said second layer overlying said at least one shielding layer;

wherein said at least one shielding layer is constructed to protect said plurality of first single crystal transistors wherein a portion of said first single crystal transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no conductive connections to said portion of said first single crystal transistors that cross said first dice lane;

wherein a portion of said second single crystal transistors is circumscribed by a second dice lane of at least 10 microns width, and there are no conductive connections to said portion of second single crystal transistors that cross said second dice lane, and wherein said second dice lane is overlaying and aligned to said first dice lane.

8. The Integrated Circuit device according to claim 7,

wherein said base wafer comprises a bulk body, and said at least one shielding layer is constructed to provide heat conduction to the bulk body.

9. The Integrated Circuit device according to claim 7, further comprising:

a bulk body, said base wafer comprising said bulk body; and

at least one thermal conducting path from at least one of said plurality of second single crystal transistors to said bulk body.

10. The Integrated Circuit device according to claim 7,

wherein the material composition of at least one of said plurality of second single crystal transistors is substantially different than the material composition of at least one of said plurality of first transistors.

11. The Integrated Circuit device according to claim 7,

wherein said second layer comprises at least one conductive pad for connecting power to said device.

12. The Integrated Circuit device according to claim 7, further comprising:

an I/O circuit adapted to interface with external devices,

wherein said I/O circuit comprises at least one of said plurality of second single crystal transistors.

13. An Integrated Circuit device, comprising:

a base wafer comprising a plurality of first single crystal transistors,

wherein said base wafer comprises a bulk body;

at least one metal layer providing interconnection between said plurality of first single crystal transistors;

at least one shielding layer overlying said at least one metal layer;

a second layer of less than 2 micron thickness, said second layer on a plane and comprising a plurality of second single crystal transistors, said second layer overlying said at least one shielding layer; and

wherein said second layer comprises at least one conductive pad for connecting power to said device

at least one heat conduction path from said at least one shielding layer to said bulk body.

14. The Integrated Circuit device according to claim 13, wherein

said at least one shielding layer is constructed to provide at least 2 times greater heat conduction in the horizontal direction than in the vertical direction.

15. The Integrated Circuit device according to claim 13, further comprising:

a first electrically conductive grid underneath said second layer, said first electrically conductive grid is constructed to provide power to at least one of said plurality of first single crystal transistors; and

a second electrically conductive grid overlaying said second single crystal transistors, said second electrically conductive grid is constructed to provide power to at least one of said plurality of second single crystal transistors;

wherein said second electrically conductive grid has a substantially higher current conduction capacity than said first electrically conductive grid.

16. The Integrated Circuit device according to claim 13, further comprising:

at least one thermal conducting path from at least one of said plurality of second single crystal transistors to the bulk body.

17. The Integrated Circuit device according to claim 13,

wherein the material composition of at least one of said plurality of second single crystal transistors is substantially different than the material composition of at least one of said plurality of first single crystal transistors.