3D semiconductor device and structure

• US 9,385,088 B2
• Filed: 02/19/2015
• Issued: 07/05/2016
• Est. Priority Date: 10/12/2009
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US14/626,563
• Publication Number:
  US 20150249053A1
• Time in Patent Office: 502 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/883 : Oxides or nitrides
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A semiconductor device including: a first layer including first transistors including at least one first monocrystalline silicon transistor channel; a second layer including second transistors including at least one second monocrystalline non-silicon transistor channel; a plurality of connection paths extending from the second transistors to the first transistors, where at least one of the connection paths includes at least one through layer via with a diameter of less than 200 nm.

Claims

1. A semiconductor device comprising:

a first layer comprising first transistors comprising at least one first monocrystalline silicon transistor channel;

a second layer comprising second transistors comprising at least one second monocrystalline non-silicon transistor channel;

a plurality of connection paths extending from said second transistors to said first transistors,

wherein at least one of said connection paths comprises at least one through layer via with a diameter of less than 200 nm.

2. A semiconductor device according to claim 1, further comprising:

a metal layer disposed between said first layer and said second layer providing interconnection between said first transistors,

wherein said metal layer comprises aluminum or copper.

3. A semiconductor device according to claim 1,

wherein at least one of said second transistors is a FinFET transistor.

4. A semiconductor device according to claim 1, further comprising:

a heat protection layer disposed between said first layer and said second layer.

5. A semiconductor device according to claim 1, further comprising:

a heat removal path between said second transistors and an external surface of said device.

6. A semiconductor device according to claim 1,

wherein at least one of said second transistors has an un-doped channel.

7. A semiconductor device according to claim 1, further comprising:

a power delivery network connected to said second transistors,

wherein said power delivery network provides a heat removal path for said second transistors.

8. A semiconductor device comprising:

a first layer comprising first transistors comprising at least one first monocrystalline silicon transistor channel;

an interconnection structure between said first transistors comprising a metal layer, said metal layer overlying said first layer;

a second layer overlaying said metal layer and comprising second transistors;

a plurality of connection paths extending from said second transistors to said first transistors, and

at least one repeater comprising said second transistors,

wherein said at least one repeater is coupled to said interconnection structure, and

wherein said at least one repeater is aligned to said first transistors with less than 200 nm misalignment, and

wherein at least one of said connection paths comprise at least one through layer via with a diameter of less than 200 nm.

9. A semiconductor device according to claim 8,

wherein said metal layer comprises aluminum or copper.

10. A semiconductor device according to claim 8,

wherein at least one of said second transistors is a FinFET transistor.

11. A semiconductor device according to claim 8, further comprising:

a heat protection layer disposed between said first layer and said second layer.

12. A semiconductor device according to claim 8, further comprising:

a heat removal path between said second transistors and an external surface of said device.

13. A semiconductor device according to claim 8,

wherein at least one of said second transistors has an un-doped channel.

14. A semiconductor device according to claim 8, further comprising:

a power delivery network connected to said second transistors,

wherein said power delivery network provides a heat removal path for said second transistors.

15. A semiconductor device comprising:

a first layer comprising first transistors, said first transistors comprising at least one first monocrystalline transistor channel;

a second layer comprising second transistors, said second transistors comprising at least one second monocrystalline transistor channel;

a plurality of connection paths extending from said second transistors to said first transistors,

wherein said first monocrystalline transistor channel is Germanium or a III-V semiconductor and said second monocrystalline transistor channel is not Germanium or a III-V semiconductor, and

wherein at least one of said connection paths comprise at least one through layer via with a diameter of less than 200 nm.

16. A semiconductor device according to claim 15, further comprising:

a metal layer disposed between said first layer and said second layer, said metal layer providing interconnection between said first transistors,

wherein said metal layer comprises aluminum or copper.

17. A semiconductor device according to claim 15,

wherein at least one of said second transistors is a FinFET transistor.

18. A semiconductor device according to claim 15, further comprising:

a heat protection layer disposed between said first layer and said second layer.

19. A semiconductor device according to claim 15, further comprising:

a heat removal path between said second transistors and an external surface of said device.

20. A semiconductor device according to claim 15, further comprising:

a power delivery network connected to said second transistors,

wherein said power delivery network provides a heat removal path for said second transistors.