Semiconductor device structures and methods of forming semiconductor structures

• US 9,385,180 B2
• Filed: 12/18/2014
• Issued: 07/05/2016
• Est. Priority Date: 06/21/2005
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Brask, Justin K., Kavalieros, Jack, Doyle, Brian S., Shah, Uday, Datta, Suman, Majumdar, Amlan, Chau, Robert S.
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US14/576,111
• Publication Number:
  US 20150102429A1
• Time in Patent Office: 565 Days
• Field of Search: 257/410
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/30617 Anisotropic liquid etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Claims

1. A nonplanar transistor, comprising:

a semiconductor body disposed on and continuous with a bulk monocrystalline silicon substrate, without an intervening insulating layer disposed between the semiconductor body and the bulk monocrystalline silicon substrate, wherein the semiconductor body comprises inwardly tapered sidewalls, and wherein charge migration in the semiconductor body is along a direction perpendicular to the sidewalls; and

a gate electrode disposed over the semiconductor body and orthogonal to the direction of charge migration.

2. The nonplanar transistor of claim 1, wherein each sidewall is flat from the top of the semiconductor body to the bottom of the semiconductor body.

3. The nonplanar transistor of claim 1, further comprising:

a high-k gate dielectric layer disposed between the semiconductor body and the gate electrode.

4. The nonplanar transistor of claim 1, wherein the gate electrode is a metal gate electrode.

5. The nonplanar transistor of claim 1, wherein each sidewall is flat from the top of the semiconductor body to the bottom of the semiconductor body, and the nonplanar transistor further comprises a high-k gate dielectric layer disposed between the semiconductor body and the gate electrode.

6. The nonplanar transistor of claim 1, wherein each sidewall is flat from the top of the semiconductor body to the bottom of the semiconductor body, and wherein the gate electrode is a metal gate electrode.

7. The nonplanar transistor of claim 1, wherein each sidewall is flat from the top of the semiconductor body to the bottom of the semiconductor body, and wherein the gate electrode is a metal gate electrode, and the nonplanar transistor further comprises a high-k gate dielectric layer disposed between the semiconductor body and the gate electrode.

8. The nonplanar transistor of claim 1, wherein the gate electrode is a metal gate electrode, and the nonplanar transistor further comprises a high-k gate dielectric layer disposed between the semiconductor body and the gate electrode.