Deep trench isolation structure layout and method of forming

• US 9,385,190 B2
• Filed: 03/04/2014
• Issued: 07/05/2016
• Est. Priority Date: 03/04/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rogers, Brent D., Pigott, John M., Gray, Randall C.
• Primary Examiner(s): Islam, Mohammad
• Assistant Examiner(s): LIU, MIKKA H
• Application Number:
  US14/196,278
• Publication Number:
  US 20150255537A1
• Time in Patent Office: 854 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The embodiments described herein provide a semiconductor device layout and method that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes a plurality of deep trench isolation structures that define and surround a first plurality of first trench-isolated regions in the substrate, and further define a second plurality of second trench-isolated regions in the substrate. The first plurality of first trench-isolated regions is arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions. Likewise, the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

a plurality of deep trench isolation structures formed in the semiconductor substrate, the plurality of deep trench isolation structures each extending at least to a buried insulator layer in the semiconductor substrate, the plurality of deep trench isolation structures defining and surrounding a first plurality of first trench-isolated regions in the substrate and a second plurality of second trench-isolated regions in the substrate, wherein

each of the first plurality of first trench-isolated regions has a first dimension along a first direction and each of the second plurality of second trench-isolated regions has a corresponding second dimension along the first direction, and where the second dimension is at least twice the first dimension,

the first plurality of first trench-isolated regions are arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions arranged along the first direction, and

the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that at least one second trench-isolated region is between consecutive first columns in the array, and wherein adjacent of the plurality of first columns and the second trench-isolated regions share common deep trench isolation structures in between, wherein each of first plurality of first trench-isolated regions includes a single semiconductor device formed within and wherein each of the second plurality of second trench-isolated regions includes at least two semiconductor devices formed within.

2. The semiconductor device of claim 1 wherein the single semiconductor device comprises a single diode and wherein the at least two semiconductor devices comprises at least one diode and at least one antifuse.

3. The semiconductor device of claim 1 wherein the plurality of deep trench isolation structures additionally define and surround a third plurality of third trench-isolated regions and a fourth plurality of fourth trench-isolated regions, the third plurality of third trench-isolated regions arranged in a column between columns of the fourth plurality of fourth trench-isolated regions, and wherein the third plurality of third trench-isolated regions are offset from the fourth plurality of fourth trench-isolated regions by an offset distance.

4. The semiconductor device of claim 3 wherein the third plurality of third trench-isolated regions are offset from the fourth plurality of fourth trench-isolated regions in the first direction.

5. The semiconductor device of claim 1 wherein the plurality of first columns are interleaved with the second trench-isolated regions along a second direction, and wherein the second direction is substantially perpendicular to the first direction.

6. The semiconductor device of claim 1 wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.

7. The semiconductor device of claim 1 wherein each of the plurality of first trench-isolated regions are substantially identical in size.

8. An antifuse array, comprising:

a semiconductor substrate; and

a plurality of deep trench isolation structures formed in the semiconductor substrate, the plurality of deep trench isolation structures each extending at least to a buried insulator layer in the semiconductor substrate, the plurality of deep trench isolation structures defining and surrounding a first plurality of first trench-isolated regions in the substrate and a second plurality of second trench-isolated regions in the substrate, wherein

each of the first plurality of first trench-isolated regions has a first dimension along a first direction and each of the second plurality of second trench-isolated regions has a corresponding second dimension along the first direction, and wherein the second dimension is at least twice the first dimension,

the first plurality of first trench-isolated regions are arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions arranged along the first direction,

the plurality of first columns are interleaved with the second plurality of second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array,

each of first plurality of first trench-isolated regions includes a single diode formed within, and

each of the second plurality of second trench-isolated regions includes at least one diode and at least one antifuse formed within.

9. The antifuse array of claim 8 wherein the plurality of deep trench isolation structures additionally define and surround a third plurality of third trench-isolated regions and a fourth plurality of fourth trench-isolated regions, the third plurality of third trench-isolated regions arranged in a column between columns of the fourth plurality of fourth trench-isolated regions, and wherein the third plurality of third trench-isolated regions are offset from the fourth plurality of fourth trench-isolated regions by an offset distance.

10. The antifuse array of claim 8 wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.

11. The antifuse array of claim 8 wherein each of the plurality of first trench-isolated regions are substantially identical in size.

12. The antifuse array of claim 8 wherein each of the second plurality of second trench-isolated regions includes a plurality of diodes, each of the plurality of diodes having an anode, and wherein the anodes of the plurality of diodes in each second trench-isolated region are coupled together.

13. A method of forming a semiconductor device, the method comprising:

providing a semiconductor substrate; and

forming a plurality of deep trench isolation structures in the semiconductor substrate, the plurality of deep trench isolation structures each extending at least to a buried insulator layer in the semiconductor substrate, the plurality of deep trench isolation structures defining and surrounding a first plurality of first trench-isolated regions in the substrate and a second plurality of second trench-isolated regions in the substrate, wherein

each of the first plurality of first trench-isolated regions has a first dimension along a first direction and each of the second plurality of second trench-isolated regions has a corresponding second dimension along the first direction, and wherein the second dimension is at least twice the first dimension,

the first plurality of first trench-isolated regions are arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions arranged along the first direction, and

wherein the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array, and wherein adjacent of the plurality of first columns and the second trench-isolated regions share common deep trench isolation structures in between; and

forming a single semiconductor device in each of first plurality of first trench-isolated regions and forming at least two semiconductor devices in each of the second plurality of second trench-isolated regions.

14. The method of claim 13 wherein the single semiconductor device comprises a single diode and wherein the at least two semiconductor devices comprises at least an antifuse and a diode.

15. The method of claim 13 wherein the plurality of deep trench isolation structures additionally define and surround a third plurality of third trench-isolated regions and a fourth plurality of fourth trench isolated regions, the third plurality of third trench-isolated regions arranged in a column between columns of the fourth plurality of fourth trench-isolated regions, and wherein the third plurality of third trench isolated regions are offset in the first direction from the fourth plurality of fourth trench-isolated regions by an offset distance.

16. The method of claim 15 wherein the plurality of first columns are interleaved with the second trench-isolated regions along a second direction, and wherein the second direction is substantially perpendicular to the first direction.

17. The method of claim 13 wherein each of the plurality of first trench-isolated regions are substantially identical in size.