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Deep trench isolation structure layout and method of forming

  • US 9,385,190 B2
  • Filed: 03/04/2014
  • Issued: 07/05/2016
  • Est. Priority Date: 03/04/2014
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a semiconductor substrate; and

    a plurality of deep trench isolation structures formed in the semiconductor substrate, the plurality of deep trench isolation structures each extending at least to a buried insulator layer in the semiconductor substrate, the plurality of deep trench isolation structures defining and surrounding a first plurality of first trench-isolated regions in the substrate and a second plurality of second trench-isolated regions in the substrate, whereineach of the first plurality of first trench-isolated regions has a first dimension along a first direction and each of the second plurality of second trench-isolated regions has a corresponding second dimension along the first direction, and where the second dimension is at least twice the first dimension,the first plurality of first trench-isolated regions are arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions arranged along the first direction, andthe plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that at least one second trench-isolated region is between consecutive first columns in the array, and wherein adjacent of the plurality of first columns and the second trench-isolated regions share common deep trench isolation structures in between, wherein each of first plurality of first trench-isolated regions includes a single semiconductor device formed within and wherein each of the second plurality of second trench-isolated regions includes at least two semiconductor devices formed within.

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