Semiconductor device having a patterned gate dielectric

• US 9,385,202 B2
• Filed: 12/19/2014
• Issued: 07/05/2016
• Est. Priority Date: 07/24/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Kuruc, Marian, Vavro, Juraj
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US14/577,044
• Publication Number:
  US 20150102403A1
• Time in Patent Office: 564 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.

Claims

1. An insulated gate semiconductor device structure comprising:

a region of semiconductor material having a major surface and a first conductivity type;

a first trench extending from the major surface;

a second trench extending from the major surface and spaced apart from the first trench;

a first dielectric layer formed along lower surfaces of both the first and second trenches and at least a portion of a first upper surface of both the first and second trenches;

a second dielectric layer formed along at least a portion of a second upper surface of both the first and second trenches but not along the first upper surfaces of both the first and second trenches, wherein the second dielectric layer is thinner than the first dielectric layer;

a first conductive electrode formed within the first trench along the first and second dielectric layers; and

a second conductive electrode formed within the second trench along the first and second dielectric layers, wherein the first and second conductive electrodes and the second dielectric layer are configured to control a channel region within the region of semiconductor material.

2. The structure of claim 1, wherein the second upper surface of the first trench is opposite to the first upper surface of the first trench, and wherein the first upper surface of the first trench has alternating portions comprising the first dielectric layer and the second dielectric layer along a length of the first trench.

3. The structure of claim 1 further comprising:

a third trench extending from the major surface between the first and second trenches;

the first dielectric layer formed along surfaces of the third trench; and

a third electrode formed within the third trench, wherein the third electrode is electrically isolated from the region of semiconductor material, and wherein the third electrode is electrically isolated from the first and second conductive electrodes.

4. The structure of claim 3, wherein the third trench is formed absent the second dielectric layer, and wherein the third electrode is configured as a shield electrode.

5. A semiconductor device comprising:

a region of semiconductor material having a first major surface;

a first trench gate structure in the region of semiconductor material and extending from the first major surface, wherein the first trench gate structure comprises a first gate electrode having a first shape in cross-sectional view;

a second trench gate structure in the region of semiconductor material and extending from the first major surface, wherein the second trench gate structure is spaced apart from the first trench gate structure, and wherein the second trench gate structure comprises a second gate electrode having a second shape in cross-sectional view;

a trench electrode structure in the region of semiconductor material and extending from the first major surface, wherein the trench electrode structure is spaced apart from the first trench gate structure and the second trench gate structure, and wherein the trench electrode structure comprises an electrode having a third shape in cross-sectional view, and wherein the third shape is different than the first shape and the second shape, and wherein the trench electrode structure is disposed laterally in between the first trench gate structure and the second trench gate structure, and wherein the electrode of the trench electrode structure is electrically isolated from the region of semiconductor material, and wherein the trench electrode structure is other than a gate electrode structure;

a base region of a first conductivity type adjacent at least the first trench gate structure;

an emitter region of a second conductivity type opposite to the first conductivity type adjacent the first trench gate structure, but not adjacent the trench electrode structure; and

a first conductive electrode electrically coupled to the emitter region.

6. The device of claim 5, wherein the second shape is different than the first shape.

7. The device of claim 5, wherein the first shape and the second shape are substantially the same.

8. The device of claim 5, wherein:

the first conductive electrode is electrically coupled to the electrode of the trench electrode structure; and

at least a portion of a top surface of the electrode of the trench electrode structure is recessed below the major surface to a depth different than that of a top surface of the first gate electrode.

9. The device of claim 5, wherein:

the region of semiconductor material comprises the second conductivity type; and

the device further comprises a doped region of the first conductivity type along a second major surface opposite to the first major surface.

10. The device of claim 5, wherein:

the first trench gate structure comprises a first dielectric layer along lower surfaces of the first trench gate structure but not along at least one upper sidewall surface of the first trench gate structure and a second dielectric layer along the at least one upper sidewall surface of the first trench gate structure; and

the trench electrode structure comprises the first dielectric layer at least along both upper sidewall surfaces of the trench electrode structure.

11. The device of claim 10, wherein the first trench gate structure comprises:

the first dielectric layer along the lower surfaces of the first trench gate structure but not along opposing upper sidewall surfaces of the first trench gate structure; and

the second dielectric layer along the opposing upper sidewall surfaces.

12. The device of claim 11, wherein the second trench gate structure comprises:

the first dielectric layer along lower surfaces of the second trench gate structure, along a first upper sidewall surface of the second trench gate structure , but not along a second upper sidewall surface of the second trench gate structure opposite of the first upper sidewall surface; and

the second dielectric layer along the second upper sidewall surface.

13. The device of claim 12, wherein:

the second upper sidewall surface faces the first trench gate structure; and

the emitter region is further disposed adjacent the second upper sidewall surface.

14. The device of claim 13, wherein the base region that adjoins the trench electrode structure is devoid of any emitter regions adjoining the trench electrode structure.

15. The device of claim 5, wherein the first conductive electrode comprises:

a via extending into the region of semiconductor material; and

a conductive fill material within the via.

16. The device of claim 15, wherein the via overlaps at least a portion of the electrode.

17. The device of claim 5, wherein the emitter region is adjacent the first trench gate structure but not adjacent at least one side of the second trench gate structure.

18. A semiconductor device comprising:

a region of semiconductor material having a first major surface and comprising a first conductivity type;

first trench gate structure in the region of semiconductor material and extending from the first major surface, wherein the first trench gate structure comprises a first gate electrode having a first shape in cross-sectional view;

a second trench gate structure in the region of semiconductor material and extending from the first major surface, wherein the second trench gate structure is spaced apart from the first trench gate structure, and wherein the second trench gate structure comprises a second gate electrode having a second shape in cross-sectional view;

a trench electrode structure in the region of semiconductor material and extending from the first major surface, wherein the trench electrode structure is spaced apart from the first trench gate structure and the second trench gate structure, and wherein the trench electrode structure comprises an electrode having a third shape in cross-sectional view, and wherein the third shape is different than the first shape and the second shape, and wherein the trench electrode structure is disposed laterally in between the first trench gate structure and the second trench gate structure, and wherein the electrode of the trench electrode structure is electrically isolate from the region of semiconductor material, and wherein the trench electrode structure is other than a gate electrode structure;

a base region of a second conductivity type opposite to the first conductivity type adjacent at least the first trench gate structure;

an emitter region of the first conductivity type adjacent the first trench gate structure but not adjacent either side of the trench electrode structure; and

a first conductive electrode electrically coupled to the emitter region.

19. The device of claim 18, wherein:

the first trench gate structure comprises a first dielectric layer along lower surfaces of the first trench gate structure but not along at least one upper sidewall surface of the first trench gate structure and a second dielectric layer along the at least one upper sidewall surface of the first trench gate structure; and

the trench electrode structure comprises the first dielectric layer at least along both upper sidewall surfaces of the trench electrode structure.

20. The device of claim 19, wherein the first trench gate structure comprises:

the first dielectric layer along the lower surfaces of the first trench gate structure but not along opposing upper sidewall surfaces of the first trench gate structure; and

the second dielectric layer along the opposing upper sidewall surfaces.