Semiconductor device

• US 9,385,230 B2
• Filed: 07/21/2015
• Issued: 07/05/2016
• Est. Priority Date: 03/25/2013
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shimomura, Akihiro, Akiyama, Yutaka, Shimomura, Saya, Nakashiba, Yasutaka
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US14/804,819
• Publication Number:
  US 20150325696A1
• Time in Patent Office: 350 Days
• Field of Search: 257/330, 257/331, 257/488, 257/409, 257/328, 257/E29.311, 257/E29.26
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

Claims

1. A semiconductor device comprising:

a first conductor layer of a first conductivity type;

a second conductor layer of the first conductivity type formed over the first conductor layer;

a third conductor layer of a second conductivity type formed over the second conductor layer;

a gate trench which passes through the third conductor layer and is formed in the second conductor layer;

a first insulating film formed on an inner wall of the gate trench so as to contact the second conductor layer;

a second insulating film formed on the inner wall of the gate trench so as to contact the third conductor layer;

a first buried conductor layer formed in the gate trench so as to contact the first insulating film;

a gate electrode formed in the gate trench so as to contact the second insulating film;

a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench; and

a fifth conductor layer of the first conductivity type formed over the third conductor layer,

wherein the first insulating film is thicker than the second insulating film.

2. The semiconductor device according to claim 1, further comprising:

a third insulating film located between the first buried conductor layer and the gate electrode.

3. The semiconductor device according to claim 1,

wherein the fourth conductor layer is in contact with the first insulating film.

4. The semiconductor device according to claim 1,

wherein a width of the fourth conductor layer is larger than a width of the first buried conductor layer.

5. The semiconductor device according to claim 1,

wherein the first buried conductor layer includes polysilicon and the fourth conductor layer is formed in the second conductor layer.

6. The semiconductor device according to claim 1, further comprising:

a second buried conductor layer of the first conductivity type is formed over the first buried conductor.

7. The semiconductor device according to claim 6,

wherein an impurity concentration of the second buried conduction layer is higher than an impurity concentration of the first buried conduction layer.

8. The semiconductor device according to claim 1, further comprising:

a drain electrode located under the first conductor layer.

9. The semiconductor device according to claim 1, further comprising:

a source electrode located over the fifth conductor layer and the second conductor layer is electrically connected to the source electrode.

10. A semiconductor device comprising:

a first conductor layer;

a second conductor layer formed over the first conductor layer;

a third conductor layer formed over the second conductor layer, the third conductor layer having a different conductivity type from the second conductor layer;

a gate trench which passes through the third conductor layer and into the second conductor layer, the gate trench having a substantially uniform width in a first direction;

a first buried conductor layer formed in the gate trench, the first buried conductor layer comprising a first upper surface, a second upper surface positioned higher than the first upper surface, and a third upper surface between the first upper surface and the second upper surface;

a gate electrode formed over the first upper surface of the first buried conductor layer and next to the third surface of the first buried conductor layer and in the gate trench; and

insulating film between the gate electrode and the third conductor layer and between the first buried conductor layer and the second conductor layer,

wherein the gate electrode has a widest width in the first direction that is less than a width of the first buried conductor layer in the first direction.