III-nitride light emitting device including porous semiconductor

• US 9,385,265 B2
• Filed: 04/12/2011
• Issued: 07/05/2016
• Est. Priority Date: 12/04/2007
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Inventors: Wierer, Jonathan J. Jr., Epler, John E.
• Primary Examiner(s): SAYADIAN, HRAYR
• Application Number:
  US13/084,679
• Publication Number:
  US 20110193059A1
• Time in Patent Office: 1,911 Days
• Field of Search: 257/97, 257/E33.025, 257/E21.119, 438/481
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body

Abstract

A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.

Claims

1. A device comprising:

a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region;

a porous III-nitride region;

a III-nitride layer comprising indium disposed between the light emitting layer and the porous III-nitride region;

a mask layer disposed between the porous III-nitride region and the III-nitride layer comprising indium; and

a plurality of openings formed in the mask layer.

2. The device of claim 1 wherein the porous III-nitride region is divided into a plurality of regions, each of the plurality of porous regions being aligned with an opening in the mask layer.

3. The device of claim 2 wherein the porous regions are separated by regions of nonporous III-nitride material having the same composition as the porous regions.

4. The device of claim 1 wherein the III-nitride layer comprising indium is one of InGaN and AlInGaN.

5. The device of claim 1 wherein the III-nitride layer comprising indium has a composition of indium equal to or less than a composition of indium in the III-nitride light emitting layer.