RRAM retention by depositing Ti capping layer before HK HfO

• US 9,385,316 B2
• Filed: 03/04/2014
• Issued: 07/05/2016
• Est. Priority Date: 01/07/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liao, Yu-Wen, Chu, Wen-Ting, Ong, Tong-Chern
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): CHO, SUNG IL
• Application Number:
  US14/196,416
• Publication Number:
  US 20150194602A1
• Time in Patent Office: 854 Days
• Field of Search: 365/148, 257/288, 257/211
• US Class Current: 1/1
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

The present disclosure relates to a resistance random access memory (RRAM) device architecture where a Ti metal capping layer is deposited before the deposition of the HK HfO resistance switching layer. Here, the capping layer is below the HK HfO layer, and hence no damage will occur during the top RRAM electrode etching. The outer sidewalls of the capping layer are substantially aligned with the sidewalls of the HfO layer and hence any damage that may occur during future etching steps will happen at the outer side walls of the capping layer that are positioned away from the oxygen vacancy filament (conductive filament) in the HK HfO layer. Thus the architecture in the present disclosure, improves data retention.

Claims

1. A resistance random access memory (RRAM) device comprising:

a variable resistance dielectric layer having a top surface and a bottom surface;

a cathode disposed over the variable resistance dielectric layer and abutting the top surface;

a metal capping layer disposed below the variable resistance dielectric layer and abutting the bottom surface; and

an anode disposed below the metal capping layer at a location vertically between the metal capping layer and a semiconductor body, wherein the anode comprises a bump protruding outward from a lower surface of the anode that faces away from the metal capping layer.

2. The RRAM device of claim 1, further comprising:

a pair of sidewall spacers arranged laterally about outer sidewalls of the cathode, wherein the cathode has a first width as measured between the outer sidewalls;

wherein the variable resistance dielectric layer and the metal capping layer each have a second width as measured between their respective outer sidewalls, wherein the second width is greater than the first width.

3. The RRAM device of claim 2, wherein the sidewall spacers comprise SiN (silicon nitride).

4. The RRAM device of claim 2, wherein outer sidewalls of the metal capping layer are spaced apart from a conductive filament region arranged under the cathode and residing within the variable resistance dielectric layer.

5. The RRAM device of claim 2, further comprising:

oxidized regions abutting outer sidewalls of the metal capping layer.

6. The RRAM device of claim 2, wherein the cathode has outer sidewalls that directly abut corresponding inner sidewalls of the sidewall spacers without oxidized regions between the cathode and sidewall spacers, and wherein the outer sidewalls of the cathode are disposed at locations near a center region of the variable resistance dielectric layer.

7. The RRAM device of claim 2, wherein outer sidewalls of the variable dielectric layer, the metal capping layer, and the anode are substantially aligned with each other.

8. The RRAM device of claim 1 wherein:

the cathode comprises a TaN (tantalum nitride) layer over a TiN (titanium nitride) layer;

the anode comprises a TaN layer;

the variable resistance dielectric layer comprises HfO₂ (hafnium oxide); and

the metal capping layer comprises Ti (titanium) or Ta (tantalum) or Hf (hafnium).

9. The RRAM device of claim 1, wherein:

the anode and the cathode have larger thicknesses than the metal capping layer.

10. The RRAM device of claim 1 further comprising:

a semiconductor base area comprising a metal interconnect structure disposed within an extremely low-k dielectric layer formed thereover

a dielectric protection layer having an open region above the metal interconnect structure, wherein sidewalls of the open region of the dielectric protection layer end above the metal interconnect structure.

17. The RRAM device of claim 1, further comprising:

a pair of sidewall spacers arranged laterally about outer sidewalls of the cathode.

18. The RRAM device of claim 1, wherein the metal capping layer has a greater width than the anode.

11. A resistance random access memory (RRAM) stack of an RRAM device comprising:

a bottom electrode comprising TaN;

a Ti (titanium) metal capping layer arranged over the bottom electrode;

a HK-HfO (high-k hafnium oxide) variable resistance dielectric layer arranged over the Ti metal capping layer;

a top electrode comprising a TaN (tantalum nitride) layer over a TiN (titanium nitride) layer;

a pair of sidewall spacers arranged laterally about outer sidewalls of the top electrode, wherein the top electrode has a first width as measured between its outer sidewalls; and

wherein the HK-HfO variable resistance dielectric layer and the Ti metal capping layer each have a second width as measured between their respective outer sidewalls, wherein the second width is greater than the first width.

12. The RRAM device of claim 11, further comprising:

a semiconductor body having a source region and a drain region horizontally separated by a channel region;

a gate structure coupled to the channel region;

a first contact and a second contact disposed above the source and drain regions, respectively;

a first metal interconnect disposed above the drain region, residing below the second contact and electrically coupled to the second contact; and

the RRAM stack formed above the first metal interconnect.

13. A method of forming a resistance random-access memory (RRAM) stack comprising:

providing a semiconductor base surface comprising a metal interconnect structure disposed within a low-k dielectric layer;

forming a dielectric protection layer having an opening that extends from an upper surface of the dielectric protection layer to the metal interconnect structure;

depositing an anode layer above the dielectric protection layer, the anode layer touching the metal interconnect structure through the opening in the dielectric protection layer;

depositing a metal capping layer above the anode layer, wherein the metal capping layer is vertically separated from a semiconductor body by the anode layer;

depositing a variable resistance dielectric layer above the metal capping; and

depositing a cathode layer above the variable resistance dielectric layer.

14. The method of claim 13, further comprising:

forming a mask over the cathode layer, the mask covering some portions of the cathode layer while leaving other regions of the cathode layer exposed;

performing a first etch to remove the exposed portions of the cathode layer and to thereby form a cathode structure; and

forming sidewall spacers about outer sidewalls of the cathode structure, wherein the sidewall spacers and cathode structure cover some portions of the variable resistance dielectric layer and leave other portions of the variable resistance dielectric layer exposed.

15. The method of claim 14, further comprising:

with the sidewall spacers and cathode structure in place, performing a second etch to remove the exposed portions of the variable resistance dielectric layer as well as underlying portions of the anode layer and the metal capping layer, to thereby form an anode structure;

wherein the second etch stops at the dielectric protection layer.

16. The method of claim 15, further comprising:

forming a second dielectric protection layer and an insulating layer covering the RRAM stack,

forming contact vias coupled to the cathode structure; and

forming metal contacts coupling the RRAM stack to a source line.

19. The method of claim 13, wherein the variable resistance dielectric layer is separated from the dielectric protection layer by the anode layer and the metal capping layer.