Delay cell, delay locked look circuit, and phase locked loop circuit

• US 9,385,699 B2
• Filed: 05/22/2015
• Issued: 07/05/2016
• Est. Priority Date: 07/24/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Dong-Hyuk, Park, Jae-Jin, Lee, Seung-Hoon
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/719,406
• Publication Number:
  US 20160028410A1
• Time in Patent Office: 410 Days
• Field of Search: 327147-149, 327156-158
• US Class Current: 1/1
• CPC Class Codes: H03K 2005/00013 Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Abstract

A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell.

Claims

1. A delay cell comprising:

a first transistor having a first terminal connected to a power supply voltage terminal, a second terminal connected to an output terminal, and a gate terminal connected to an input terminal; and

a second transistor having a first terminal connected to a ground terminal, a second terminal connected to the output terminal, and a gate terminal connected to the input terminal,

wherein each of the first and second transistors has a fully depleted silicon-on-insulator (FD-SOI) structure, and at least one of a first control voltage and a second control voltage is applied to at least one of bodies of the first transistor and the second transistors to adjust a delay time of the delay cell.

2. The delay cell of claim 1, wherein the first transistor is a P-type Metal Oxide Semiconductor (PMOS) transistor and the second transistor is an N-type MOS (NMOS) transistor.

3. The delay cell of claim 1, wherein each of the first transistor and second transistor comprises:

a body layer;

a buried insulation layer on the body layer;

a pair of impurity regions disposed on the buried insulation layer to function as source/drain regions;

a semiconductor layer disposed between the pair of impurity regions in contact with the buried insulation layer;

a gate insulation layer on a top surface of the semiconductor layer opposite to the buried insulation layer; and

a gate electrode on the gate insulation layer.

4. The delay cell of claim 3, wherein the body layer of the first transistor is N-type and the pair of impurity regions of the first transistor are P-type, and

the body layer of the second transistor is P-type and the pair of impurity regions of the second transistor are N-type.

5. The delay cell of claim 1, wherein the first terminals of the first and second transistors are source terminals and the second terminals of the first and second transistors are drain terminals.

6. The delay cell of claim 1, wherein each of the first and second transistors has an ultra-thin body and buried oxide (UTBB) FD-SOI structure.

7. The delay cell of claim 1, further comprising:

a third transistor coupled between the power supply voltage terminal and the first terminal of the first transistor; and

a fourth transistor coupled between the ground terminal and the first terminal of the second transistor,

wherein the third transistor has a first terminal connected to the power supply voltage terminal, a second terminal connected to the first terminal of the first transistor, and a gate terminal to which a third control voltage is applied, and

the fourth transistor has a first terminal connected to the ground terminal, a second terminal connected to the first terminal of the second transistor, and a gate terminal to which a fourth control voltage is applied.

8. The delay cell of claim 7, further comprising a fifth transistor and a sixth transistor,

wherein the fifth transistor has a first terminal connected to the power supply voltage terminal, a second terminal connected to a node, and a gate terminal connected to the node and the gate terminal of the third transistor, and

the sixth transistor has a first terminal connected to the ground terminal, a second terminal connected to the node, and a gate terminal to which the fourth control voltage is applied.

9. A delay locked loop (DLL) circuit comprising:

a delay circuit that receives a reference clock signal and includes series connected delay cells that applies a delay to the reference clock signal to generated a delayed buffered version of the reference clock signal;

a phase detector that receive the reference clock signal and a feed-back clock signal and generates a first signal corresponding to a phase difference between the feed-back clock signal and the reference clock signal; and

a control circuit that generates a first control signal that defines the delay applied to the reference clock signal in response to the first signal,

wherein the first control signal is applied to a body of at least one of the transistors constituting at least one of the delay cells, the at least one of the transistors having a fully depleted silicon-on-insulator (FD-SOI) structure.

10. The DLL circuit of claim 9, wherein each of the series-connected delay cells has a single ended configuration including an inverter or a differential delay circuit.

11. The DLL circuit of claim 9, wherein the control circuit additionally generates a second control signal that compensates for variation of at least one of a process, voltage, and temperature, and

the second control signal is applied to a gate terminal of a transistor controlling current flowing through the series-connected delay cells.

12. The DLL circuit of claim 9, wherein the control circuit additionally generates a second control signal that compensates for variation of at least one of a process, voltage, and a temperature, and

the second control signal is applied to a body of at least another one of the transistors constituting the at least one of the delay cells, and the first control signal is applied to a gate terminal of a transistor controlling current flowing through the series-connected delay cells.

13. The DLL circuit of claim 9, wherein each of the series-connected delay cells comprises:

a first transistor having a first terminal connected to a power supply voltage terminal, a second terminal connected to an output terminal, and a gate terminal connected to an input terminal; and

a second transistor having a first terminal connected to a ground terminal, a second terminal connected to the output terminal, and a gate terminal connected to the input terminal,

wherein each of the first and second transistors has a fully depleted silicon-on-insulator (FD-SOI) structure, and

the first control signal is applied to the body of the first transistor.

14. The DLL circuit of claim 9, further comprising:

a replica delay circuit that receives the delayed buffered version of the reference clock signal as the feed-back signal from the delay circuit and compensates for an essential delay time of a system incorporating the DLL circuit.

15. The DLL circuit of claim 14, wherein the replica delay circuit is a delay model circuit associated with the essential delay time.

16. A phase locked loop (PLL) circuit comprising:

a phase detector that receives a reference clock signal and a divided feed-back clock signal and generates a first signal corresponding to a phase difference between the divided feed-back clock signal and the reference clock signal;

a control circuit that generates a first control signal that defines a delay applied to the reference clock signal in response to the first signal;

a voltage controlled oscillator including delays cells and applying the delay to the reference clock signal to generate the feed-back clock signal; and

a divider that receives the feed-back clock signal to generate the divided feed-back clock signal,

wherein the first control signal is applied to a body of at least one of the transistors constituting at least one of the delay cells, the at least one of the transistors having a fully depleted silicon-on-insulator (FD-SOI) structure.

17. The PLL of claim 16, wherein the first signal is a phase control signal including an up-signal or a down-signal.

18. The PLL of claim 17, wherein the control circuit increases a voltage level of the first control signal in response to the up-signal, or decreases a voltage level of the first control signal in response to the down-signal.

19. The PLL of claim 17, wherein the control circuit generates a coarse control signal that roughly tunes the delay applied by the voltage-controlled oscillator, and a fine control signal that accurately tunes the delay applied by the voltage-controlled oscillator.

20. The PLL of claim 17, wherein the control circuit generates a second control signal that compensates for variation of at least one of a process, voltage, and temperature.