Methodology to avoid gate stress for low voltage devices in FDSOI technology

• US 9,385,708 B2
• Filed: 03/17/2014
• Issued: 07/05/2016
• Est. Priority Date: 03/17/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Agrawal, Ankit
• Primary Examiner(s): Ho, Hoang-Quan
• Application Number:
  US14/216,701
• Publication Number:
  US 20150263726A1
• Time in Patent Office: 841 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors

Abstract

An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

Claims

1. A device comprising:

a first semiconductor substrate;

a dielectric layer on the first semiconductor substrate;

a second semiconductor substrate on the dielectric layer and separated from the first semiconductor substrate by the dielectric layer;

a gate dielectric layer on the second semiconductor substrate;

a plurality of transistors each respectively including;

a gate terminal on the gate dielectric layer and separated from the second semiconductor substrate by the gate dielectric layer;

a channel region in the second semiconductor substrate below the gate terminal; and

a source and drain region in the second semiconductor substrate, the source and the gate terminal being electrically connected;

a voltage source coupled to the first semiconductor substrate and configured to turn the plurality of transistors on or off by applying a high voltage or a low voltage to the first semiconductor substrate.

2. The device of claim 1 wherein the plurality of transistors includes a PMOS transistor and an NMOS transistor.

3. The device of claim 2 wherein the drains of the PMOS and NMOS transistors are coupled together.

4. The device of claim 3 wherein the NMOS and PMOS transistors are an inverter, the drains of the NMOS and PMOS transistors being an output of the inverter, and the first semiconductor substrate is an input of the inverter.

5. The device of claim 1 wherein the channel regions of the plurality of transistors have a length less than or equal to 32 nm.

6. The device of claim 5 wherein at least one of the plurality of transistors is configured to operate with a drain to source voltage greater than or equal to 3 V.

7. The device of claim 1 comprising a data input pad electrically coupled to the first semiconductor substrate.

8. The device of claim 1 wherein the gate dielectric layer is less than 5 nm thick.

9. The device of claim 8 wherein the dielectric layer is greater than 15 nm thick.

10. An integrated circuit die comprising:

a first semiconductor substrate;

a dielectric layer on the first semiconductor substrate;

a second semiconductor substrate on the dielectric layer and separated from the first semiconductor substrate by the dielectric layer;

a gate dielectric layer on the second semiconductor substrate;

a Schmitt trigger including;

a gate terminal on the gate dielectric layer and separated from the second semiconductor substrate by the gate dielectric layer;

a channel region in the second semiconductor substrate below the gate terminal; and

a source and drain region in the second semiconductor substrate, the source and the gate terminal being electrically connected;

a voltage source coupled to the first semiconductor substrate and configured to turn the transistors on or off by applying a high voltage or a low voltage to the first semiconductor substrate.

11. A digital circuit, comprising:

a power supply;

a plurality of dual gate transistors coupled in series between the power supply and a ground, each dual gate transistor having a source, a drain, a front side gate, and a back gate, source terminals of some of the transistors being coupled to their respective front side gates;

an input coupled to all of the back gates; and

an output coupled between at least two of the drains.

12. The circuit of claim 11 wherein the dual gate transistors are fully-depleted silicon-on-insulator (FDSOI) devices.

13. The circuit of claim 11 wherein a low voltage signal appears at the output of the digital circuit in response to a high voltage signal applied to the input, and a high voltage signal appears at the output in response to a low voltage signal applied at the input.

14. The circuit of claim 11 wherein a gate dielectric of the back gates is substantially thicker than a gate dielectric of the front side gates.

15. The circuit of claim 14 wherein the gate dielectric of the back gates is a buried oxide layer in a silicon substrate.

16. The circuit of claim 11 wherein the plurality of dual gate transistors includes a first PMOS transistor and a first NMOS transistor.

17. The circuit of claim 16, further comprising:

a second dual gate PMOS transistor and a second dual gate NMOS transistor coupled in series with the first dual gate transistors; and

a selected reference voltage coupled to front side gates of the second transistors,

wherein the input is further coupled to back gates of the second transistors; and

wherein the output is coupled between drains of the second PMOS and NMOS transistors.

18. The circuit of claim 17 wherein a voltage of the power supply exceeds a breakdown voltage of the front side gates.

19. The circuit of claim 18 wherein the power supply voltage exceeds 3 V.

20. The circuit of claim 17 wherein two different reference voltages are coupled to the front side gates of the second PMOS and NMOS transistors.