Phase-locked loop (PLL)
First Claim
1. A phase-locked loop (PLL), comprising:
- a clock adjuster configured to;
receive an initial clock signal having an initial frequency;
receive a mode control signal; and
responsive to a change in a phase error signal of the PLL being below an error threshold, modify the initial clock signal to a first clock signal based on the mode control signal, the first clock signal having a first frequency; and
a loop filter configured to generate a loop filter output signal based on the first clock signal, the loop filter output signal controlling a bandwidth of the PLL.
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Accused Products
Abstract
A phase-locked loop (PLL) is provided. The PLL comprises a clock adjuster configured to receive an initial clock signal having an initial frequency and a mode control signal. The clock adjuster is configured to modify the initial clock signal into a modified clock signal based on the mode control signal. The PLL is configured such that a loop bandwidth is equal to a specified bandwidth. When the modified clock signal is changed, a loop gain of a loop filter is adjusted such that the loop bandwidth is substantially equal to the specified bandwidth. When the modified clock signal is changed, an oscillator tuning word (OTW) signal is modified into a normalized OTW signal such that the loop bandwidth is substantially equal to the specified bandwidth.
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Citations
20 Claims
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1. A phase-locked loop (PLL), comprising:
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a clock adjuster configured to; receive an initial clock signal having an initial frequency; receive a mode control signal; and responsive to a change in a phase error signal of the PLL being below an error threshold, modify the initial clock signal to a first clock signal based on the mode control signal, the first clock signal having a first frequency; and a loop filter configured to generate a loop filter output signal based on the first clock signal, the loop filter output signal controlling a bandwidth of the PLL. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for operating a phase-locked loop (PLL), comprising:
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comparing a change in a phase error signal of the PLL to an error threshold; responsive to determining that the change is below the error threshold, modifying an initial clock signal of the PLL having an initial frequency to a first clock signal having a first frequency to alter power usage of the PLL; and responsive to the modifying an initial clock signal, modifying a bandwidth of the PLL to a specified bandwidth. - View Dependent Claims (16, 17)
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18. A method for operating a phase-locked loop (PLL), comprising:
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receiving an initial clock signal having an initial frequency; receiving a mode control signal; responsive to a change in a phase error signal of the PLL being below an error threshold, modifying the initial clock signal to generate a first clock signal having a first frequency, the first frequency corresponding to the initial frequency divided by a divisor selected based upon the mode control signal; and generating a loop filter output signal based on the first clock signal, the loop filter output signal controlling a bandwidth of the PLL. - View Dependent Claims (19, 20)
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Specification