Speculative finish of instruction execution in a processor core

• US 9,389,867 B2
• Filed: 08/31/2015
• Issued: 07/12/2016
• Est. Priority Date: 11/16/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chadha, Sundeep, Lloyd, Bryan, Nguyen, Dung Q., Ray, David S., Stolt, Benjamin W.
• Primary Examiner(s): SNYDER, STEVEN G
• Application Number:
  US14/840,997
• Publication Number:
  US 20150370573A1
• Time in Patent Office: 316 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.

Claims

1. A method of data processing, comprising:

tracking high latency operations of a processor core in entries of a data structure associated with an execution unit of a processor core;

in the execution unit, prior to completion of a high latency operation tracked by an entry of the data structure, speculatively finishing execution of an instruction dependent on the high latency operation, wherein the speculatively finishing includes reporting an identifier of the entry to completion logic of the processor core and freeing a resource in an execution pipeline of the execution unit utilized by the instruction;

the completion logic recording a dependence of the instruction on the high latency operation and committing an execution result of the instruction to an architected state of the processor core only after successful completion of the high latency operation; and

in response to unsuccessful completion of the high latency operation;

the completion logic flushing the instruction without committing the execution result to the architected state; and

the processor core reissuing the instruction with an indication that speculative finishing of the instruction is inhibited.

2. The method of claim 1, wherein:

the processor core includes a completion table including a plurality of entries for tracking instructions, wherein each of the plurality of entries includes a bit vector including multiple bits each corresponding to a respective one of the entries in the data structure that tracks high latency operations;

the recording includes setting a bit in the bit vector corresponding to the entry of the data structure that tracks the high latency operation on which the instruction is dependent.

3. The method of claim 2, and further comprising:

in response to successful completion of the high latency operation, removing a condition of instruction completion from multiple instructions tracked by the completion table by resetting, in all of the multiple bit vectors, the bit corresponding to the entry of the data structure that tracks the high latency operation.

4. The method of claim 1, wherein:

the processor core includes an upper level cache;

the execution unit is a load-store execution unit (LSU) that executes memory access instructions;

the data structure is a load miss queue (LMQ);

the instruction is a load-type instruction; and

the high latency operation is a read memory access operation that misses in the upper level cache.

5. The method of claim 4, wherein:

the read memory access operation requests a target memory block; and

the speculatively finishing includes speculatively finishing the load-type instruction in response to receipt by the LSU of a critical data word of the target memory block.

6. The method of claim 1, and further comprising:

after the speculatively finishing and prior to committing the execution result, utilizing the execution resource to execute another instruction.