Multithreaded processor with plurality of scoreboards each issuing to plurality of pipelines

• US 9,389,869 B2
• Filed: 01/06/2011
• Issued: 07/12/2016
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tran, Thang
• Primary Examiner(s): Caldwell, Andrew
• Assistant Examiner(s): Mehta, Jyoti
• Application Number:
  US12/986,136
• Publication Number:
  US 20110099355A1
• Time in Patent Office: 2,014 Days
• Field of Search: 712/216, 712/217
• US Class Current: 1/1
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/324 using program counter relative addressing
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3888 controlled by a single instruction for multiple threads [SIMT] in parallel

Abstract

A multi-threaded microprocessor for processing instructions in single threaded mode and multithreaded modes. The microprocessor includes instruction dependency scoreboards, instruction input coupling circuits for selectively feeding the first and second instruction dependency scoreboards; output coupling logic having first and second instruction issue outputs; first and second execute pipelines respectively coupled to the instruction issue outputs, the first execute pipeline for executing a first program thread and the second execute pipeline for executing a second program thread, independent of the first program thread; and a control logic circuit for causing dual issue of instructions from the first program thread, by the first dependency scoreboard, to both the first execute pipeline and said second execute pipeline.

Claims

1. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:

first and second instruction dependency scoreboards;

first and second instruction input coupling circuits each having a coupling input and first and second coupling outputs and together to selectively feed the first and second instruction dependency scoreboards;

output coupling logic having first and second coupling inputs fed by said first and second instruction dependency scoreboards, and having first and second instruction issue outputs;

first and second execute pipelines respectively coupled to said instruction issue outputs of said output coupling logic, said first execute pipeline for executing a first program thread and said second execute pipeline for executing a second program thread, independent of said first program thread; and

a control logic circuit for controlling said first instruction input coupling circuit and said output coupling logic for causing dual issue of instructions from said first program thread, by said first instruction dependency scoreboard, to both said first execute pipeline and said second execute pipeline, the control logic circuit supplying a first selector signal to the first instruction input coupling circuit and to the output coupling logic, the first selector signal causing dual issue of instructions from the first program thread, by the first instruction dependency scoreboard, to both the first execute pipeline and the second execute pipeline.

2. The multi-threaded microprocessor claimed in claim 1 further comprising first and second instruction queues respectively coupled to the coupling inputs of said first and second instruction input coupling circuits.

3. The multi-threaded microprocessor claimed in claim 1 wherein said control logic circuit supplies a second selector signal to said second instruction input coupling circuit and to said output coupling logic, said second selector signal causes dual issue of instructions from said second program thread, by said second instruction dependency scoreboard, to both said first execute pipeline and said second execute pipeline.

4. The multi-threaded microprocessor claimed in claim 1 further comprising first and second decode pipelines respectively coupled to a corresponding coupling input of said first and second instruction input coupling circuits.

5. The multi-threaded microprocessor claimed in claim 1 further comprising scoreboard routing circuitry and in which the first and second instruction dependency scoreboards share said scoreboard routing circuitry together.