Memory redundancy to replace addresses with multiple errors

• US 9,389,954 B2
• Filed: 02/26/2014
• Issued: 07/12/2016
• Est. Priority Date: 02/26/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Pelley, Perry H., Hoekstra, George P., Ramaraju, Ravindraraj
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US14/190,949
• Publication Number:
  US 20150242269A1
• Time in Patent Office: 867 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

A method and apparatus are provided for error correction of a memory by using a first memory (18), second memory (14), and redundant memory (19) to perform error correction code (ECC) processing on data retrieved from the first memory (18) by using the redundant memory (19) to replace entries in the second memory (14) having repeat addresses, thereby freeing entries in the second memory (14) for use in detecting and managing errors identified by the ECC processing.

Claims

1. A method comprising:

initiating a read operation of a first memory to retrieve data from a specified address;

performing an error correction code (ECC) process on the data to detect if the data is erroneous and to provide corrected data;

detecting if a second memory has exceeded a storage threshold level;

storing the specified address and corrected data in the second memory in an available entry when the second memory has not exceeded the storage threshold level; and

transferring one or more redundant entries from the second memory to a redundant memory when the second memory has exceeded the storage threshold level.

2. The method of claim 1, wherein the first memory is one of either a dynamic random access memory (DRAM) or a static random access memory (SRAM).

3. The method of claim 1, where the second memory comprises a content addressable memory (CAM) for storing a plurality of entries, each comprising an address field and data field.

4. The method of claim 1, where detecting if the second memory has exceeded the storage threshold level comprises detecting if a content addressable memory (CAM) has a predetermined threshold number of CAM entries.

5. The method of claim 4, further comprising identifying the one or more entries in the second memory for transfer to a redundant element of the first memory by scanning the CAM to identify CAM entries having a repeat address.

6. The method of claim 4, further comprising,

selecting a CAM entry comprising CAM entry data to be written to a redundant element of the first memory and a CAM entry address;

activating a redundant element in the redundant memory to be addressed by a first portion of the CAM entry address; and

writing corrected CAM entry data to the redundant element in the redundant memory at a second portion CAM entry address.

7. The method of claim 6, further comprising writing selected data not requiring correction to the redundant element from the first memory from an address corresponding to the first portion of the CAM entry address.

8. The method of claim 6, further comprising removing each CAM entry having the first portion of the CAM entry address.

9. The method of claim 1, further comprising outputting the corrected data to a data processor.

10. The method of claim 1, further comprising transferring all entries from the second memory to the redundant memory upon detecting a predetermined event where the first memory and redundant memory are inactive.

11. The method of claim 1, further comprising transferring all entries from the second memory to a non-volatile memory upon detecting a predetermined power down or reset event.

12. A memory comprising:

a first memory organized in an array of rows and columns for addressing data read and write operations;

a second memory organized as a plurality of entries for storing data, each entry comprising an address value and corrected data;

a spare memory comprising one or more redundant elements for storing data at specified addresses;

an error correction control circuit for performing error correction on data stored in the first memory at a specified address to generate corrected data, and for storing the corrected data and specified address in an entry in the second memory; and

a circuit coupled to the second memory and spare memory that is configured to detect if the second memory has exceeded a storage threshold level, and to transfer one or more redundant entries from the second memory to the spare memory when the second memory has exceeded the storage threshold level.

13. The memory of claim 12, where spare memory is formed in a redundant memory region of the first memory.

14. The memory of claim 12, where the second memory comprises a content addressable memory (CAM).

15. The memory of claim 14, where the circuit further comprises control logic for detecting if the second memory has a predetermined threshold number of CAM entries.

16. The memory of claim 15, where the circuit further comprises control logic for identifying one or more entries in the second memory for transfer to a redundant element of the spare memory by scanning the second memory to identify CAM entries having a repeat address.

17. The memory of claim 14, where the circuit is configured to transfer one or more redundant entries from the second memory to the spare memory by selecting a CAM entry from the second memory comprising CAM entry data to be written to a redundant element of the spare memory and a CAM entry address, activating a redundant element in the spare memory to be addressed by a first portion of the CAM entry address, and writing corrected CAM entry data to the redundant element in the spare memory at a second portion CAM entry address.

18. The memory of claim 12, where the circuit is configured to transfer one or more redundant entries from the second memory to the spare memory by transferring all entries from the second memory to the spare memory upon detecting a predetermined event where the first memory and spare memory are inactive.

19. The memory of claim 12, where the circuit is configured to all entries from the second memory to a non-volatile memory upon detecting a predetermined power down or reset event.

20. A system comprising:

a random access memory (RAM) array;

a content addressable memory (CAM) array;

an address decoder for initiating a read operation of the RAM array to retrieve data from a specified address;

control circuitry for performing an error correction code (ECC) process on data retrieved from the RAM array to detect if the data is erroneous, to provide corrected data, and to store the specified address and corrected data to the CAM array; and

a CAM replacement circuit for detecting if the CAM array has exceeded a storage threshold level by scanning the CAM array to identify CAM entries having a repeat address, where the CAM replacement circuit transfers one or more redundant entries from the CAM array to a spare memory when the CAM array has exceeded the storage threshold level.