Hybrid memory management

• US 9,390,004 B2
• Filed: 05/30/2014
• Issued: 07/12/2016
• Est. Priority Date: 05/28/2008
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Radke, William, Murray, Michael, Furuhjelm, Martin Ragnar, Geldman, John
• Primary Examiner(s): Bertram, Ryan
• Application Number:
  US14/291,644
• Publication Number:
  US 20140281177A1
• Time in Patent Office: 774 Days
• Field of Search: 711/103, 711/154, 711/165
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

Claims

1. An electronic system comprising:

a processor having a standard interface;

a memory device coupled to the processor at least in part through the standard interface, the memory device comprising;

a first array of memory cells of a first type;

a second array of memory cells of a second type different from the first type; and

control circuitry configured to store data determined by the control circuitry to be stored in the first array of memory cells of the first type having a first lower density and to store data determined by the control circuitry to be stored in the second array of memory cells of the second type having a second higher density;

wherein the processor is adapted to instruct the control circuitry how to determine, based on the nature of the data, whether to store data in the first array of memory cells or the second array of memory cells and wherein the control circuitry assigns a logical block address to the one of the first and second memory arrays based upon the number of spare locations in the memory array of the first type of memory cells.

2. The electronic system of claim 1, wherein the first array of memory cells are single level memory cells and the second array of memory cells are multi-level memory cells.

3. The electronic system of claim 1, wherein the first array of memory cells comprises single level memory cells configured to store a first number of bits per memory cell and the second array of memory cells comprises multi-level memory cells configured to store a second number of bits per memory cell, and wherein the second number of bits is greater than the first number of bits.

4. The electronic system of claim 1, wherein the control circuitry is coupled to a usage block.

5. The electronic system of claim 2 wherein the usage block is maintained by the processor.

6. The electronic system of claim 5 wherein the usage block is a separate memory device.

7. The electronic system of claim 6 wherein the usage block is stored in the first array of memory cells.

8. The electronic system of claim 6 wherein the control circuitry is configured to assign a logical block address to one of the first array of memory cells and the second array of memory cells based on information in the usage block in support of maintaining the number of spare locations in the memory array of the first type.

9. The electronic system of claim 8 wherein the logical block address is assigned to the array of memory cells of the first type if the usage is not below a predetermined threshold.

10. The electronic system of claim 9 wherein the logical block address is assigned to the array of memory cells of the second type if the usage is not above a certain threshold.

11. The electronic system of claim 1 wherein the standard interface is selected from the group consisting of a universal serial bus and a hard disk drive interface.

12. The electronic system of claim 2 wherein the interface and control circuitry are configured to emulate a hard disk drive.

13. The electronic device of claim 2 wherein the control circuitry determines that data to be stored in a data cache of the hard disk drive is stored in the single level memory cells and data to be stored in magnetic media of the hard disk drive is stored in the second array of multi-level memory cells.