Systems and methods of storing data

• US 9,390,774 B2
• Filed: 10/22/2014
• Issued: 07/12/2016
• Est. Priority Date: 07/22/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Sharon, Eran, Alrod, Idan, Litsyn, Simon
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US14/521,001
• Publication Number:
  US 20150043276A1
• Time in Patent Office: 629 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method includes, when using a binary cache in an multi-level cell (MLC) flash memory splitting a codeword corresponding to a data page into multiple data pages and storing the multiple data pages into multiple single level cell (SLC) pages of the binary cache for subsequent storage into a single wordline of the MLC flash memory.

Claims

1. A data storage device comprising:

a multi-level cell (MLC) flash memory; and

a single level cell (SLC) binary cache,

wherein a controller of the data storage device is configured to split a codeword corresponding to a data page into multiple data pages and to store the multiple data pages into multiple SLC pages of the SLC binary cache for subsequent storage into a single wordline of the MLC flash memory, wherein a length of the codeword differs from a size of an SLC page of the multiple SLC pages.

2. The data storage device of claim 1, wherein the length of the codeword exceeds the size of the SLC page.

3. The data storage device of claim 1, wherein for at least one of the multiple data pages first and second portions of the codeword are stored into first and second SLC pages of the SLC pages.

4. The data storage device of claim 1, wherein the MLC flash memory is configured to store B bits per cell, wherein B is a positive integer, wherein B codewords are stored in more than B SLC pages of the binary cache, and wherein the B codewords are copied from the SLC binary cache to the single wordline of the MLC flash memory.

5. The data storage device of claim 1, wherein the single wordline of the MLC flash memory is associated with a first logical page, a second logical page, and a third logical page.

6. The data storage device of claim 1, further comprising a memory, wherein the memory includes the MLC flash memory and the SLC binary cache.

7. The data storage device of claim 1, wherein the controller is further configured to receive the codeword from an error correction coding (ECC) engine.

8. The data storage device of claim 7, wherein the controller is further configured to store the codeword to the SLC binary cache.

9. The data storage device of claim 1, further comprising an error correction coding (ECC) engine configured to generate the codeword.

10. The data storage device of claim 1, wherein the SLC binary cache includes a plurality of SLC pages.

11. A method comprising:

in a binary cache of a multi-level cell (MLC) flash memory included in a data storage device that includes a controller;

splitting a codeword corresponding to a data page into multiple data pages; and

storing the multiple data pages into multiple single level cell (SLC) pages of the binary cache for subsequent storage into a single wordline of the MLC flash memory, wherein a length of the codeword differs from a size of an SLC page of the multiple SLC pages.

12. The method of claim 11, wherein the length of the codeword exceeds the size of the SLC page.

13. The method of claim 11, wherein for at least one of the multiple data pages first and second portions of the codeword are stored into first and second SLC pages of the SLC pages.

14. The method of claim 11, wherein the MLC flash memory is configured to store B bits per cell, wherein B is a positive integer, wherein B codewords are stored in more than B SLC pages of the binary cache, and further comprising copying the B codewords from the more than B SLC pages to the single wordline of the MLC flash memory.

15. The method of claim 11, wherein the single wordline of the MLC flash memory is associated with multiple logical pages.

16. The method of claim 11, further comprising receiving the codeword at the controller.

17. The method of claim 16, wherein the codeword is received at the controller from an error correction coding (ECC) engine.

18. The method of claim 11, wherein the codeword is based on data received from a host device.

19. The method of claim 11, further comprising:

storing a first portion of the codeword in a first SLC page of the multiple SLC pages; and

storing a second portion of the codeword in a second SLC page of the multiple SLC pages.