Scalable interconnect structures with selective via posts

• US 9,391,019 B2
• Filed: 03/20/2014
• Issued: 07/12/2016
• Est. Priority Date: 03/20/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kobrinsky, Mauro, Andryushchenko, Tatyana, Chebiam, Ramanan, Yoo, Hui Jae
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US14/220,814
• Publication Number:
  US 20150270211A1
• Time in Patent Office: 845 Days
• Field of Search: 438/622, 438/641, 257/758
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.

Claims

1. An integrated circuit (IC) interconnect structure, comprising:

a conductive interconnect feature embedded within a first dielectric material disposed over a substrate;

a via recess overlapping a sidewall of the interconnect feature;

a conductive via post disposed in direct contact with a top surface of the interconnect feature; and

a second dielectric material disposed within the via recess and in direct contact with the sidewall of the interconnect feature, wherein the via recess defines a non-planarity in the first dielectric material, or in an intervening dielectric material disposed between the first dielectric material and the second dielectric material.

2. The IC interconnect structure of claim 1, wherein

the via recess defines a non-planarity in the first dielectric material that exposes the sidewall of the interconnect feature;

the conductive via post is substantially absent from the interconnect feature sidewall;

a top surface of the first dielectric layer beyond a lateral dimension of the via recess is planar with the top surface of the interconnect feature; and

the first and second dielectric materials form an interface demarking the via recess.

3. The IC interconnect structure of claim 1, wherein the first and second dielectric materials form an interface demarking the via recess;

and

wherein the intervening dielectric material is disposed between the first and second dielectric material in regions where the via recess is absent, and further disposed over the top surface of the interconnect feature in regions where the via post is absent.

4. The IC interconnect structure of claim 1, wherein:

the interconnect feature comprises a fill metal of a first composition, and an interconnect liner of a second composition cladding the sidewalls of the fill metal;

the via post is in contact with the fill metal; and

the second dielectric material disposed within the recess is in contact with the interconnect liner.

5. The IC interconnect structure of claim 1, wherein the interconnect feature comprises:

a fill metal of a first metal composition suitable for electroless formation of the via post material; and

an interconnect liner cladding sidewalls of the fill metal, the liner being of a second composition unsuitable for electroless formation of the via post material.

6. The IC interconnect structure of claim 1, wherein:

the via post comprises at least one of Ni, Cu, Co, Ru, Pd, Pt, or Au, and is doped with P, C, W, or B impurities; and

the interconnect feature comprises;

a fill metal; and

an interconnect liner cladding sidewalls of the fill metal, the liner further comprising a metal nitride, a metal oxide, or a non-metallic dielectric having a composition distinct from the first dielectric material.

7. The IC interconnect structure of claim 1, wherein:

the via post is embedded within the second dielectric material, with a thickness of the second dielectric material exceeding a vertical height of the via post.

8. The IC interconnect structure of claim 1, wherein:

the via post is embedded within the second dielectric material, with a thickness of the second dielectric material exceeding a vertical height of the via post; and

the second dielectric material comprises a dielectric stack including;

a conformal base layer disposed within the via recess and cladding the via post; and

a non-conformal top layer disposed over the base layer, the top layer having a thickness sufficient to cover a top surface of the via post.

9. The IC interconnect structure of claim 1, further comprising:

a second conductive interconnect feature disposed on a top surface of the via post, the second conductive feature extending beyond an edge of the top via post surface and contacting a portion of a sidewall of the via post.

10. The IC interconnect structure of claim 1, wherein:

the conductive interconnect feature is one of a pair of interconnect features embedded within the first dielectric material and spaced laterally apart by a first space;

the via recess is disposed within the first space; and

a bottom of the via post in contact with a top surface of a first of the pair of interconnect features is laterally spaced apart from a top surface of the second of the pair of interconnect structures by at least the first space.

11. A method of fabricating an integrated circuit (IC) interconnect structure, the method comprising:

forming a conductive interconnect feature embedded within a first dielectric material over a substrate;

patterning a via opening that exposes a top surface and a sidewall of the conductive interconnect feature;

forming a conductive via post in direct contact with the top surface of the interconnect feature selectively relative to the exposed sidewall; and

depositing a second dielectric material within the via opening, over the first dielectric material, in direct contact with the exposed conductive interconnect feature sidewall, and over a sidewall of the via post, wherein the via opening defines a non-planarity in the first dielectric material, or in an intervening dielectric material disposed between the first dielectric material and the second dielectric material.

12. The method of claim 11, wherein:

forming the conductive interconnect feature further comprises cladding a fill metal of a first metal composition suitable for catalyzing a subsequent electroless deposition with a liner material unsuitable for catalyzing the subsequent electroless deposition; and

forming the conductive via post further comprises electrolessly depositing a via metal on the catalytic fill metal without depositing the via metal on the non-catalytic liner.

13. The method of claim 11, wherein depositing the second dielectric material further comprises:

conformally depositing a base dielectric layer onto the sidewall of the conductive interconnect feature, and over a sidewall of the via post; and

non-conformally depositing a top dielectric layer over the base dielectric layer to planarize a top surface of the top dielectric layer over a top surface of the via post.

14. The method of claim 11, further comprising depositing an intervening dielectric material over the top surface of the interconnect feature and over the first dielectric material;

wherein;

patterning the via opening further comprises etching through the intervening dielectric material to expose a portion of the interconnect feature top surface and form a via recess in the first dielectric material adjacent to the interconnect feature that exposes the conductive interconnect feature sidewall; and

wherein depositing the second dielectric material comprises depositing the second dielectric material over the intervening dielectric material.

15. The method of claim 11, further comprising:

surrounding the via post with the second dielectric material;

etching a second via opening into the second dielectric material exposing a top surface of the via post, the second via opening extending beyond an edge of the via post top surface, and exposing a portion of a sidewall of the via post; and

depositing a second interconnect feature within the second via opening, the second interconnect feature contacting the top surface and sidewall of the via post.

16. An integrated circuit (IC) interconnect structure, comprising:

a pair of first conductive interconnect features embedded within a first dielectric material disposed over a substrate and spaced laterally apart by a first space;

a conductive via post disposed in direct contact with a top surface one of the first conductive interconnect features;

a second conductive interconnect feature embedded within a second dielectric material disposed over the first dielectric material, and disposed in direct contact with a top surface of the via post, wherein the second interconnect feature is laterally misaligned from the via post with a bottom surface of the second interconnect feature overlapping the first space and separated from the first dielectric material by at least a portion of the height of the via post.

17. The IC structure of claim 16, further comprising an intervening dielectric material disposed over the top surface of the pair of first interconnect features in regions where the via post is absent, and wherein the intervening dielectric material is further absent from at least a portion of the first space.

18. The IC structure of claim 16, wherein:

the pair of first interconnect features comprises a pair of interconnect lines including a fill metal of a first composition, and an interconnect liner of a second composition cladding the sidewalls of the fill metal;

the second interconnect feature comprises a third interconnect line including the fill metal, and the interconnect liner cladding the sidewalls of the fill metal;

the via post is in contact with the fill metal of one of the pair of first interconnect features and is in contact with an interconnect liner of the third interconnect line; and

the via post has a third composition, distinct from the interconnect fill metal and cladding.

19. The IC structure of claim 16, wherein the via post comprises at least one of Ni, Cu, Co, Ru, Pd, Pt, or Au, and is doped with P, C, W, or B impurities.