Chip package and method for fabricating the same

• US 9,391,021 B2
• Filed: 07/21/2009
• Issued: 07/12/2016
• Est. Priority Date: 08/11/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Jahan, Bilkis
• Assistant Examiner(s): Doan, Nga
• Application Number:
  US12/506,278
• Publication Number:
  US 20100013082A1
• Time in Patent Office: 2,548 Days
• Field of Search: 438/108, 438/110, 438/113, 257/778, 257/620
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 : the item being a discrete passive component
• CPC Class Codes: H01L 2224/24227 : the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next forming a patterned circuit layer over the polymer material and connected to the metal bump, and then forming a tin-containing ball over the patterned circuit layer and connected to the patterned circuit layer.

Claims

1. A chip package comprising:

a first semiconductor chip having a first surface, said first semiconductor chip comprising a passivation layer defining an opening exposing a contact pad;

a first polymer layer having a planar surface and a polymer surface opposite said planar surface, in which a portion of said first polymer layer is coupled to said first surface and sidewalls of said first semiconductor chip;

a first conductive interconnect having a coupling surface for coupling to said contact pad and a second surface opposite said coupling surface, in which said second surface of said first conductive interconnect is co-planar with said polymer surface of said first polymer layer opposite said first surface of said first semiconductor chip, wherein said first conductive interconnect comprises an adhesion/barrier layer directly on said first polymer layer and said contact pad, a conductive seed layer directly on said adhesion/barrier layer and an electroplated conductive layer directly on said seed layer, wherein a first sidewall of said electroplated conductive layer is flush with a first sidewall of said adhesion/barrier layer and a first sidewall of said seed layer, and a second sidewall opposite said first sidewall of said electroplated conductive layer is flush with a second sidewall of said adhesion/barrier layer and a second sidewall of said seed layer;

a second polymer layer coupled to said first polymer layer on said polymer surface;

a conductive layer having conductive elements within and directly on a surface of said second polymer layer and directly on said second surface opposite said coupling surface of said first conductive interconnect, and across an edge of said first semiconductor chip; and

a third polymer layer on said conductive layer, on said second polymer layer and across said edge of said first semiconductor chip.

2. The chip package of claim 1 further comprising a second semiconductor chip coupled to said first polymer layer, wherein said second semiconductor chip is coupled to said first semiconductor chip through said conductive layer.

3. The chip package of claim 1 further comprising a second conductive interconnect on a contact point of said conductive layer within an opening in said second polymer layer, wherein said second conductive interconnect is coupled to said contact point through said opening, wherein said second conductive interconnect comprises a tin-containing layer coupled to said contact point.

4. The chip package of claim 1 further comprising a substrate coupled to said first polymer layer.

5. The chip package of claim 1, wherein said first semiconductor chip further comprises a conductive trace coupled to said first semiconductor substrate, wherein said conductive trace comprises a second copper layer having a thickness between 1 and 20 micrometers, wherein said first copper layer is further directly on said second copper layer.

6. The chip package of claim 5, wherein said conductive trace further comprises a titanium-containing layer coupled to said second copper layer.

7. The chip package of claim 5, wherein said first semiconductor chip further comprises a third polymer layer coupled to said first semiconductor substrate, wherein said conductive trace is further on said third polymer layer, wherein said third polymer layer has a thickness between 3 and 15 micrometers.

8. A chip package comprising:

a first semiconductor chip having a first surface, said first semiconductor chip comprising a passivation layer having an opening exposing a contact pad;

a first polymer layer having a planar surface and a polymer surface opposite said planar surface, in which a portion of said first polymer layer is coupled to said first surface and sidewalls of said first semiconductor chip;

a first conductive interconnect having a coupling surface for coupling to said contact pad and a second surface opposite said coupling surface, in which said second surface of said first conductive interconnect is co-planar with said polymer surface of said first polymer layer opposite said first surface of said semiconductor chip, wherein said first conductive interconnect comprises an adhesion/barrier layer directly on said first polymer layer and said contact pad, a conductive first seed layer directly on said adhesion/barrier layer and an electroplated conductive layer directly on said seed layer, wherein a first sidewall of said electroplated conductive layer is flush with a first sidewall of said adhesion/barrier layer and a first sidewall of said seed layer, and a second sidewall opposite said first sidewall of said electroplated conductive layer is flush with a second sidewall of said adhesion/barrier layer and a second sidewall of said seed layer;

a second polymer layer coupled to said first polymer layer on said polymer surface;

a conductive layer having conductive elements within and directly on a surface of said second polymer layer and directly on said second surface opposite said coupling surface of said first conductive interconnect, and across an edge of said first semiconductor chip, wherein said conductive layer comprises a second conductive seed layer coupled to said surface of said second polymer layer and across said edge of said first semiconductor chip; and

a third polymer layer on said conductive layer, on said second polymer layer and across said edge of said first semiconductor chip.

9. The chip package of claim 8 further comprising a second semiconductor chip coupled to said first polymer layer, wherein said second semiconductor chip is coupled to said first semiconductor chip through said conductive layer.

10. The chip package of claim 8 further comprising a second conductive interconnect on a contact point of said conductive layer within an opening in said second polymer layer, wherein said second conductive interconnect is coupled to said contact point through said opening, wherein said second conductive interconnect comprises a tin-containing layer coupled to said contact point.

11. The chip package of claim 8, wherein said second conductive seed layer has a thickness between 5 and 100 micrometers.

12. The chip package of claim 8 further comprising a substrate coupled to said first polymer layer.

13. The chip package of claim 8, wherein said first semiconductor chip further comprises a conductive trace coupled to said semiconductor substrate, wherein said conductive trace comprises a third copper layer having a thickness between 1 and 20 micrometers, wherein said first copper layer is further directly on said third copper layer.

14. The chip package of claim 13, wherein said conductive trace further comprises a titanium-containing layer coupled to said third copper layer.

15. The chip package of claim 13, wherein said first semiconductor chip further comprises a third polymer layer coupled to said semiconductor substrate, wherein said conductive trace is further on said third polymer layer, wherein said third polymer layer has a thickness between 3 and 15 micrometers.

16. A chip package comprising:

a first semiconductor chip having a first surface, said first semiconductor chip comprising a passivation layer having an opening exposing a contact pad;

a first polymer layer having a planar surface and a polymer surface opposite said planar surface, in which a portion of said first polymer layer is coupled to said first surface and sidewalls of said first semiconductor chip;

a first conductive interconnect having a coupling surface for coupling to said contact pad and a second surface opposite said coupling surface, in which said second surface of said first conductive interconnect is co-planar with said polymer surface of said first polymer layer opposite said first surface of said semiconductor chip, said first conductive interconnect comprising an adhesion/barrier layer directly on said first polymer layer and said contact pad, a conductive seed layer directly on said adhesion/barrier layer and an electroplated conductive layer directly on said seed layer, wherein a first sidewall of said electroplated conductive layer is flush with a first sidewall of said adhesion/barrier layer and a first sidewall of said seed layer, and a second sidewall opposite said first sidewall of said electroplated conductive layer is flush with a second sidewall of said adhesion/barrier layer and a second sidewall of said seed layer;

a second polymer layer coupled to said first polymer layer on said polymer surface;

a conductive layer having conductive elements within and directly on a surface of said second polymer layer and directly on said second surface opposite said coupling surface of said conductive interconnect, and across an edge of said first semiconductor chip;

a second semiconductor chip coupled to said first semiconductor chip through said conductive layer; and

a third polymer layer on said conductive layer, on said surface of said second polymer layer and across said edge of said first semiconductor chip.