CMOS structures and processes based on selective thinning

• US 9,391,076 B1
• Filed: 12/18/2014
• Issued: 07/12/2016
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Gregory, Paul, Thompson, Scott E., Hoffmann, Thomas, Scudder, Lance, Sridharan, Urupattur C., Zhao, Dalong, Ranade, Pushkar, Duane, Michael
• Primary Examiner(s): Enad, Christine
• Application Number:
  US14/574,896
• Time in Patent Office: 572 Days
• Field of Search: 438/275
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

Claims

1. A semiconductor chip, comprising:

a substrate having a semiconducting surface comprising a first layer formed directly on a second layer, the semiconducting surface having formed therein a plurality of active regions extending through the first layer and the second layer, the plurality of active regions comprising at least a first active region and a second active region, the first layer comprising a substantially undoped layer, and the second layer comprising a highly doped screening layer, a first gate insulating film formed directly on the first layer in the first active region, a second gate insulating film formed directly on the first layer in the second active region; and

a first semiconductor device comprising the first gate insulating film formed in the first active region and a second semiconductor device comprising the second gate insulating film formed in the second active region,

wherein a thickness of the first layer in the first active region and a thickness of the first layer in the second active region are different, wherein a thickness of the second layer in the first active region and a thickness of the second layer in the second active region are substantially the same, wherein a position of a boundary between the first layer and the second layer for each of the first active region and the second active region is substantially the same throughout the substrate, and wherein the first layer in the first active region and the first layer in the second active region are common undoped epitaxial layer of a single semiconductor material.

2. The semiconductor chip of claim 1, wherein the semiconductor material is silicon.

3. The semiconductor chip of claim 1, wherein a difference between the thickness of the first layer in the first active region and a thickness of the first layer in the second active region is between about 1 nm and 10 nm.

4. The semiconductor chip of claim 1, wherein a difference between the thickness of the first layer in the first active region and a thickness of the first layer in the second active region is between about 1 nm and 5 nm.

5. The semiconductor chip of claim 1, further comprising trench regions separating the plurality of active regions, the trench regions being filled with an electrical insulator material, wherein a step height between the electrical insulator material in the trench regions and adjacent portions of the semiconducting surface is substantially the same across the substrate.

6. The semiconductor chip of claim 1, wherein the first active region and the second active region are active regions of a same conductivity type, wherein a dopant concentration in the second layer is substantially the same in the first active region and the second active region, wherein:

the first and the second gate structures having substantially identical properties, and wherein at least one electrical characteristic of the first semiconductor device and the second semiconductor device is different.

7. The semiconductor ship of claim 6, wherein the at least one electrical characteristic comprises at least one of a threshold voltage target, a leakage current target, a subthreshold swing target, or a drain-induced barrier lowering target.