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Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

  • US 9,391,079 B2
  • Filed: 09/17/2015
  • Issued: 07/12/2016
  • Est. Priority Date: 11/29/2007
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

    a floating body region for storing charge indicating a state of said semiconductor memory cell; and

    a back-bias region;

    wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels;

    wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line; and

    wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string.

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