Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

• US 9,391,079 B2
• Filed: 09/17/2015
• Issued: 07/12/2016
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/856,943
• Publication Number:
  US 20160005741A1
• Time in Patent Office: 299 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

a floating body region for storing charge indicating a state of said semiconductor memory cell; and

a back-bias region;

wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels;

wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line; and

wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string.

2. The integrated circuit of claim 1, wherein said number of said at least one contact is less than said number of semiconductor memory cells.

3. The integrated circuit of claim 1, wherein said semiconductor memory cells are connected in series.

4. The integrated circuit of claim 1, wherein said semiconductor memory cells are connected in parallel.

5. The integrated circuit of claim 1, wherein said integrated circuit is fabricated on a bulk silicon substrate.

6. The integrated circuit of claim 1, wherein said number of said at least one contact is two.

7. The integrated circuit of claim 1, wherein said semiconductor memory cells further comprise first and second conductive regions interfacing with said floating body region.

8. The integrated circuit of claim 1, wherein each said semiconductor memory cell further comprises a gate insulated from said floating body region.

9. The integrated circuit of claim 1, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

10. The integrated circuit of claim 9, wherein a majority of said semiconductor memory cells are contactless semiconductor memory cells.

11. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

a floating body region for storing charge; and

a back bias region;

wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels;

wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;

wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and

wherein said at least one control line is connected to a read circuitry.

12. The integrated circuit of claim 11, wherein said number of said at least one contact is less than said number of said semiconductor memory cells.

13. The integrated circuit of claim 11, wherein said semiconductor memory cells are connected in series.

14. The integrated circuit of claim 11, wherein said semiconductor memory cells are connected in parallel.

15. The integrated circuit of claim 11, wherein said integrated circuit is fabricated on a bulk silicon substrate.

16. The integrated circuit of claim 11, wherein said number of said at least one contact is two.

17. The integrated circuit of claim 11, wherein said semiconductor memory cells further comprise first and second conductive regions interfacing with said floating body region.

18. The integrated circuit of claim 11, wherein each said semiconductor memory cell further comprises a gate insulated from said floating body region.

19. The integrated circuit of claim 11, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

20. The integrated circuit of claim 19, wherein a majority of said semiconductor memory cells are contactless semiconductor memory cells.