Memory bit cell for reduced layout area

• US 9,391,080 B1
• Filed: 04/28/2015
• Issued: 07/12/2016
• Est. Priority Date: 04/28/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kim, Juhan, Rashed, Mahbub
• Primary Examiner(s): Nguyen, Cuong Q
• Application Number:
  US14/698,066
• Time in Patent Office: 441 Days
• Field of Search: 438/152
• US Class Current: 1/1
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.

Claims

1. A method comprising:

providing first color structures, in a metal1 (M1) layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges;

providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges;

forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge; and

forming an array of four bit cells including a first bit cell at a lower left position, a second bit cell at a lower right position, a third bit cell at an upper left position, and a fourth bit cell at an upper right position, wherein a layout of the second bit cell is a mirror image of a layout of the first bit cell, a layout of the third bit cell is same as the layout of the second bit cell, and a layout of the fourth bit cell is same as the layout of the first bit cell.

2. The method according to claim 1, further comprising:

providing the first color structures by forming them concurrently by a first patterning process.

3. The method according to claim 2, further comprising:

providing the second color structures by forming them concurrently by a second patterning process.

4. The method according to claim 1, wherein forming the bit cell comprises:

providing a first tip edge of the first ground line adjacent to a first tip edge of the first power line;

providing a first tip edge of the first latch line adjacent to a first tip edge of the second latch line; and

providing a first tip edge of the second ground line adjacent to a first tip edge of the second power line.

5. The method according to claim 4, wherein forming the bit cell further comprises:

providing a second tip edge of the first power line opposing a first tip edge of the second bit line;

providing a second tip edge of the first latch line adjacent to a first side edge of the first word line;

providing a second tip edge of the second latch line adjacent to a first side edge of the second word line;

providing a first tip edge of the second word line adjacent to a first side edge of the second ground line; and

providing a second tip edge of the second power line opposing a first tip edge of the first bit line.

6. The method according to claim 5, wherein forming the bit cell further comprises:

forming the first ground line, first power line, and second bit line tip to tip along a first edge of the bit cell;

forming the first bit line, second power line, and second ground line tip to tip along a second edge of the bit cell opposite the first edge; and

forming the first and second latch lines tip to tip between the first and second edges of the bit cell.

7. The method according to claim 1, wherein a space between a first color structure tip edge or side edge and a second color structure tip edge or side edge is less than a space between two tip edges, two side edges, or a tip edge and a side edge of a same color structure.

8. The method according to claim 7, wherein the space between the first color structure tip edge adjacent to the second color structure tip edge is less than the space between two adjacent tip edges of the same color structure.

9. The method according to claim 1, further comprising:

providing the first word line for sharing by the first bit cell and the second bit cell; and

providing another second word line for sharing by the third bit cell and the fourth bit cell, wherein a second tip edge of the first word line is adjacent to a first tip edge of another second word line.

10. The method according to claim 1, further comprising:

providing contacts to directly connect the first color structures and the second color structures to a gate structure or active regions.

11. A method comprising:

providing first color structures, in a metal1 (M1) layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges;

providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges;

forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge, and wherein a space between the first color structure tip edge adjacent to the second color structure tip edge is less than a space between two adjacent tip edges of a same color structure; and

forming an array of four bit cells including a first bit cell at a lower left position, a second bit cell at a lower right position, a third bit cell at an upper left position, and a fourth bit cell at an upper right position, wherein a layout of the second bit cell is a mirror image of a layout of the first bit cell, a layout of the third bit cell is same as the layout of the second bit cell, and a layout of the fourth bit cell is same as the layout of the first bit cell.

12. The method according to claim 11, wherein forming the bit cell comprises:

providing a first tip edge of the first ground line adjacent to a first tip edge of the first power line;

providing a first tip edge of the first latch line adjacent to a first tip edge of the second latch line;

providing a first tip edge of the second ground line adjacent to a first tip edge of the second power line;

providing a second tip edge of the first power line opposing a first tip edge of the second bit line;

providing a second tip edge of the first latch line adjacent to a first side edge of the first word line;

providing a second tip edge of the second latch line adjacent to a first side edge of the second word line;

providing a first tip edge of the second word line adjacent to a first side edge of the second ground line;

providing a second tip edge of the second power line opposing a first tip edge of the first bit line;

forming the first ground line, first power line, and second bit line tip to tip along a first edge of the bit cell;

forming the first bit line, second power line, and second ground line tip to tip along a second edge of the bit cell opposite the first edge;

forming the first and second latch lines tip to tip between the first and second edges of the bit cell;

providing the first word line for sharing by the first bit cell and the second bit cell; and

providing another second word line for sharing by the third bit cell and the fourth bit cell, wherein a second tip edge of the first word line is adjacent to a first tip edge of another second word line.