Semiconductor device and manufacturing method thereof

• US 9,391,095 B2
• Filed: 12/12/2013
• Issued: 07/12/2016
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Maruyama, Hotaka, Oikawa, Yoshiaki, Tochibayashi, Katsuaki
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): DEHNE, AARON A
• Application Number:
  US14/104,264
• Publication Number:
  US 20140099752A1
• Time in Patent Office: 943 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02472 Oxides
• CPC Class Codes: H01L 21/02483 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer. By fourth heat treatment, hydrogen is supplied at least to an interface between the second oxide semiconductor layer and the oxide insulating layer.

Claims

1. A semiconductor device comprising:

a first layer comprising an oxide that comprises indium and zinc;

a second layer over the first layer, the second layer comprising an oxide that comprises indium and zinc;

a third layer over the second layer, the third layer comprising an oxide;

a gate electrode, wherein the gate electrode and the first to third layers overlap with each other; and

an interlayer insulating layer comprising hydrogen over the third layer,

wherein the second layer has a crystallinity,

wherein a carrier concentration of the first layer is less than 1×

10¹⁸/cm³, and

wherein a carrier concentration of the second layer is less than 1×

10¹⁸/cm³.

2. The semiconductor device according to claim 1,

wherein the oxide comprised in the first layer is an In—

Zn—

O, and

wherein the oxide comprised in the second layer is an In—

Ga—

Zn—

O.

3. The semiconductor device according to claim 1, wherein the gate electrode is located below the first to third layers.

4. The semiconductor device according to claim 1, wherein the gate electrode is located over the first to third layers.

5. The semiconductor device according to claim 1, wherein the second layer comprises a region having c-axis oriented in a direction substantially perpendicular to a surface of the second layer.

6. The semiconductor device according to claim 1, wherein the interlayer insulating layer comprising hydrogen is a nitride insulating layer comprising hydrogen.

20. The semiconductor device according to claim 1,

wherein the carrier concentration of the first layer is at least 1×

10¹²/cm³, and

wherein the carrier concentration of the second layer is at least 1×

10¹²/cm³.

7. A semiconductor device comprising:

a first layer comprising an oxide that comprises indium and zinc;

a second layer over the first layer, the second layer comprising an oxide that comprises indium and zinc;

a third layer over the second layer, the third layer comprising an oxide;

a gate electrode, wherein the gate electrode and the first to third layers overlap with each other;

an interlayer insulating layer comprising hydrogen over the third layer;

a source electrode over the second layer, the source electrode electrically connected to the second layer; and

a drain electrode over the second layer, the drain electrode electrically connected to the second layer,

wherein the third layer is located over the source electrode and the drain electrode,

wherein the second layer has a crystallinity,

wherein a carrier concentration of the first layer is less than 1×

10¹⁸/cm³, and

wherein a carrier concentration of the second layer is less than 1×

10¹⁸/cm³.

8. The semiconductor device according to claim 7,

wherein the oxide comprised in the first layer is an In—

Zn—

O, and

wherein the oxide comprised in the second layer is an In—

Ga—

Zn—

O.

9. The semiconductor device according to claim 7, wherein the gate electrode is located below the first to third layers.

10. The semiconductor device according to claim 7, wherein the gate electrode is located over the first to third layers.

11. The semiconductor device according to claim 7, wherein the second layer comprises a region having c-axis oriented in a direction substantially perpendicular to a surface of the second layer.

12. The semiconductor device according to claim 7, wherein the interlayer insulating layer comprising hydrogen is a nitride insulating layer comprising hydrogen.

19. The semiconductor device according to claim 7, wherein one of the source electrode and the drain electrode overlaps with the first to third layers.

21. The semiconductor device according to claim 7,

wherein the carrier concentration of the first layer is at least 1×

10¹²/cm³, and

wherein the carrier concentration of the second layer is at least 1×

10¹²/cm³.

13. A semiconductor device comprising:

a first layer comprising an oxide that comprises indium and zinc;

a second layer over the first layer, the second layer comprising an oxide that comprises indium and zinc;

a third layer over the second layer, the third layer comprising an oxide;

a gate electrode, wherein the gate electrode and the first to third layers overlap with each other;

an interlayer insulating layer comprising hydrogen over the third layer;

a source electrode over the third layer, the source electrode electrically connected to the second layer; and

a drain electrode over the third layer, the drain electrode electrically connected to the second layer,

wherein the second layer has a crystallinity,

wherein a carrier concentration of the first layer is less than 1×

10¹⁸/cm³, and

wherein a carrier concentration of the second layer is less than 1×

10¹⁸/cm³.

14. The semiconductor device according to claim 13,

wherein the oxide comprised in the first layer is an In—

Zn—

O, and

wherein the oxide comprised in the second layer is an In—

Ga—

Zn—

O.

15. The semiconductor device according to claim 13, wherein the gate electrode is located below the first to third layers.

16. The semiconductor device according to claim 13, wherein the gate electrode is located over the first to third layers.

17. The semiconductor device according to claim 13, wherein the second layer comprises a region having c-axis oriented in a direction substantially perpendicular to a surface of the second layer.

18. The semiconductor device according to claim 13, wherein the interlayer insulating layer comprising hydrogen is a nitride insulating layer comprising hydrogen.

22. The semiconductor device according to claim 13,

wherein the carrier concentration of the first layer is at least 1×

10¹²/cm³, and

wherein the carrier concentration of the second layer is at least 1×

10¹²/cm³.