Power semiconductor device and method of fabricating the same

• US 9,391,137 B2
• Filed: 06/09/2015
• Issued: 07/12/2016
• Est. Priority Date: 11/28/2014
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, In Su
• Primary Examiner(s): Tobergte, Nicholas
• Application Number:
  US14/734,326
• Publication Number:
  US 20160155794A1
• Time in Patent Office: 399 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

Provided are a power semiconductor device and method of fabricating the same, in particular a power semiconductor device such as an Insulated Gate Bipolar Transistor (IGBT) including a cell region with a trench structure formed to include a dummy trench and a first trench and a termination region with a termination ring formed surrounding the cell region. Such a power semiconductor device is designed to operable with high power conditions such as when an operating voltage is 600 V, 1200 V and so on.

Claims

1. A power semiconductor device comprising:

a substrate;

a trench structure situated in the substrate and comprising first trenches and dummy trenches formed adjacent to the first trenches;

a first well region of a second conductivity type situated between the first trenches;

a base region of a first conductivity type situated on the first well region;

a source region of the second conductivity type and a first contact region of the first conductivity type situated in the base region;

gate insulating layers situated in the first trenches and the dummy trenches;

gate electrodes situated on the gate insulating layers;

a field stop layer situated below the base region;

a collector layer and a drain electrode situated below the field stop layer; and

a dummy cell region situated between the first trenches and the dummy trenches,

wherein the dummy cell region has no channel region.

2. The power semiconductor device of claim 1, further comprising:

a cell region, a transition region and a termination region located in the substrate;

a first termination ring of the first conductivity type having a first depth surrounding the cell region, situated in the transition region; and

a second termination ring adjacent to the first termination ring, situated in the termination region, and

wherein the first termination ring has a width larger than that of the second termination ring.

3. The power semiconductor device of claim 2, further comprising:

a second well region of the second conductivity type having a doping concentration higher than that of the semiconductor substrate and that is situated adjacent to the second termination ring.

4. The power semiconductor device of claim 1,

wherein the first trenches and the dummy trenches have a trench depth deeper than that of the first well region.

5. The power semiconductor device of claim 1, further comprising:

an emitter electrode connected to the first termination ring, the source region and the first contact region;

a gate terminal electrically connected to the gate electrode; and

a field plate situated over the substrate and connected to the second termination ring.

6. The power semiconductor device of claim 5,

wherein a second contact region of the first conductivity type is situated in the first termination ring and is electrically connected to the emitter electrode.

7. The power semiconductor device of claim 1, wherein the substrate comprises a first surface and a second surface opposite to the first surface.

8. A manufacturing method of forming the power semiconductor device according to claim 1, the method comprising:

forming the substrate to comprise a first epi layer of low doping concentration and a second epi layer of high doping concentration.

9. The manufacturing method of claim 8,

wherein the substrate comprises a first surface and a second surface opposite to the first surface, and

wherein forming the field stop layer on the back of the substrate is performed by conducting a back grinding process on a second surface of the semiconductor substrate and by exposing the second epi layer.

10. The manufacturing method of claim 8, wherein forming the gate electrode in the trench structure comprises

depositing a polysilicon layer with a top surface in the trench structure;

oxidizing a top surface of the polysilicon layer to form an oxidized surface layer of the polysilicon layer;

removing the oxidized surface layer using wet-etching; and

performing an etch-back process to form the gate electrode.

11. A power semiconductor device comprising:

a substrate, comprising a cell region, a transition region and a termination region located in the substrate;

first trenches and dummy trenches located adjacent to the first trenches, situated in the substrate, wherein the first trenches and the dummy trenches each comprise a gate insulating layer that comprises a gate electrode;

a well region of a second conductivity type situated between the first trenches comprising a base region of a first conductivity type situated on the first well region, wherein the base region comprises a source region of the second conductivity type and a first contact region of the first conductivity type, situated in the base region;

a field stop layer situated below the base region;

a collector layer and a drain electrode situated below the field stop layer; and

a dummy cell region situated between the first trenches and the dummy trenches,

wherein the dummy cell region has no channel region.

12. The power semiconductor device of claim 11, further comprising:

a first termination ring of the first conductivity type having a first depth surrounding the cell region, formed in the transition region; and

a second termination ring adjacent to the first termination ring, formed in the termination region, and

wherein the first termination ring has a width larger than that of the second termination ring.

13. The power semiconductor device of claim 11, wherein the substrate comprises a first surface and a second surface opposite to the first surface.

14. The power semiconductor device of claim 11, further comprising:

a second well region of the second conductivity type having a doping concentration higher than that of the semiconductor substrate and that is situated adjacent to the second termination ring.

15. The power semiconductor device of claim 11,

wherein the first trenches and the dummy trenches have a trench depth deeper than that of the first well region.

16. The power semiconductor device of claim 11, further comprising:

an emitter electrode connected to the first termination ring, the source region and the first contact region;

a gate terminal electrically connected to the gate electrode; and

a field plate situated over the substrate and connected to the second termination ring.

17. The power semiconductor device of claim 16,

wherein a second contact region of the first conductivity type is situated in the first termination ring and is electrically connected to the emitter electrode.

18. A method of forming a power semiconductor device comprising:

preparing a semiconductor substrate, wherein the substrate comprises a first epi layer of low doping concentration and a second epi layer of high doping concentration, wherein the substrate is divided into a termination region, a transition region, and a cell region;

forming a first termination ring on the transition region or the termination region of the substrate;

forming a first well region in the cell region that overlaps with the first termination ring;

forming trench structures to have a certain depth in the substrate, comprising first trenches and dummy trenches;

forming gate insulating layers and gate electrodes in the trench structures;

forming a base region of a first conductivity type situated on the first well region;

forming a source region of the second conductivity type and a first contact region of the first conductivity type situated in the base region;

forming a field stop layer situated below the base region;

forming a collector layer and a drain electrode situated below the field stop layer; and

forming a dummy cell region situated between the first trenches and the dummy trenches,

wherein the dummy cell region has no channel region.

19. The method of claim 18, wherein the first termination ring is formed by ion injecting an impurity, performing a first mask process, and performing a first annealing.

20. The method of claim 19, wherein the first well region is formed using a second mask process and a second annealing.

21. The method of claim 18, wherein forming the trench structures comprises using a hard mask layer comprising 3 layers of insulating film.

22. The method of claim 18, wherein the first trenches and the dummy trenches have a trench depth deeper than that of the first well region.

23. The method of claim 18, further comprising forming a second termination ring, wherein the first termination ring has a greater width than the second termination ring.

24. The method of claim 18, further comprising depositing a polysilicon layer with a top surface in the trench structure;

oxidizing a top surface of the polysilicon layer to form an oxidized surface layer of the polysilicon layer;

removing the oxidized surface layer using wet-etching; and

performing an etch-back process to form the gate electrodes.