Semiconductor device with self-charging field electrodes

• US 9,391,149 B2
• Filed: 06/19/2013
• Issued: 07/12/2016
• Est. Priority Date: 06/19/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weber, Hans, Hirler, Franz
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Hillman, Damian A
• Application Number:
  US13/921,935
• Publication Number:
  US 20140374842A1
• Time in Patent Office: 1,119 Days
• Field of Search: 257/409
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes a drift region of a first doping type, a junction between the drift region and a device region, and a field electrode structure in the drift region. The field electrode structure includes a field electrode, a field electrode dielectric adjoining the field electrode, arranged between the field electrode and the drift region, and having an opening, and at least one of a field stop region and a generation region. The semiconductor device further includes a coupling region of a second doping type complementary to the first doping type. The coupling region is electrically coupled to the device region and coupled to the field electrode.

Claims

1. A semiconductor device, comprising:

a drift region of a first doping type;

a junction between the drift region and a device region;

a plurality of field electrode structures spaced apart from each other in a current flow direction of the semiconductor device in the drift region, each of the plurality of field electrode structures comprising;

a field electrode; and

a coupling region of a second doping type complementary to the first doping type, the coupling region being electrically coupled to the device region and coupled to the field electrode of each of the plurality of field electrode structures,

wherein each of the plurality of field electrode structures further comprises;

a field electrode dielectric adjoining the field electrode, arranged between the field electrode and the drift region, and having an opening; and

at least one of a field stop region and a generation region.

2. The semiconductor device of claim 1, wherein the coupling region adjoins at least one of the field electrode, the field stop region, the generation region, and the field electrode dielectric.

3. The semiconductor device of claim 1, wherein the coupling region adjoins the field electrode structure only in a region of the field electrode dielectric.

4. The semiconductor device of claim 1, wherein the field stop region has the first doping type, and is more highly doped than the drift region.

5. The semiconductor device of claim 1, wherein the field stop region connects the field electrode to at least one of the drift region and the coupling region through the opening of the field electrode dielectric.

6. The semiconductor device of claim 1, wherein the field stop region is at least partially arranged within the field electrode dielectric.

7. The semiconductor device of claim 6, wherein the field stop region is completely arranged within the field electrode dielectric.

8. The semiconductor device of claim 1, wherein a contact region is arranged between the field electrode and the field stop region.

9. The semiconductor device of claim 1, wherein the field stop region completely separates the field electrode from the drift region.

10. The semiconductor device of claim 1, wherein a section of the field electrode adjoins the drift region.

11. The semiconductor device of claim 1, wherein the at least one of the field stop region and the generation region does not extend more than 200 nm beyond the field electrode dielectric into the drift region in a direction perpendicular to a current flow direction of the semiconductor device.

12. The semiconductor device of claim 1, wherein the at least one of the field stop region and the generation region does not extend beyond the field electrode dielectric in a direction perpendicular to a current flow direction of the semiconductor device.

13. The semiconductor device of claim 1, wherein the generation region connects the field electrode to the drift region through the opening of the field electrode dielectric.

14. The semiconductor device of claim 1, wherein the generation region is arranged in the field electrode.

15. The semiconductor device of claim 1, wherein the generation region is at least partially arranged within the field electrode dielectric.

16. The semiconductor device of claim 1, wherein the generation region is completely arranged within the field electrode dielectric.

17. The semiconductor device of claim 1, wherein the generation region includes an interface region between the field electrode and the drift region.

18. The semiconductor device of claim 1, wherein the generation region comprises a void.

19. The semiconductor device of claim 1, wherein the field electrode includes at least one material selected from the group consisting of:

a metal;

a metal semiconductor compound;

monocrystalline semiconductor material comprising dopant atoms;

a polycrystalline semiconductor material comprising dopant atoms; and

a monocrystalline semiconductor material comprising foreign material atoms or crystal defects.

20. The semiconductor device of claim 19, wherein the dopant atoms are dopant atoms of one of the first and second doping type.

21. The semiconductor device of claim 1,

wherein the field electrode dielectric has a length extending in a current flow direction of the semiconductor device, and has a width extending in a direction perpendicular to the current flow direction, and

wherein a ratio between the length and the width is higher than 1.

22. The semiconductor device of claim 1, wherein the opening of the field electrode dielectric is located in the direction of the junction.

23. The semiconductor device of claim 1, wherein the at least one field electrode structure comprises a shielding region arranged distant to the opening of the field electrode dielectric in a current flow direction of the semiconductor device.

24. The semiconductor device of claim 1, wherein the at least one of the field stop region, the generation region and the field electrode is implemented such that it adjoins a field electrode dielectric of a neighboring field electrode structure.

25. The semiconductor device of claim 1, wherein the semiconductor device is implemented as an MOS transistor, wherein the device region is a semiconductor region of a second doping type and forms a body region, and wherein the MOS transistor further comprises:

a source region, wherein the body region is arranged between the drift region and the source region;

a drain region, wherein the drift region is arranged between the drain region and the body region; and

a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric.

26. The semiconductor device of claim 1, wherein the semiconductor device is implemented as a bipolar diode, and wherein the device region is a semiconductor region of a second doping type and forms an emitter region.

27. The semiconductor device of claim 1, wherein the semiconductor device is implemented as a Schottky diode, and wherein the device region is a Schottky region.

28. The semiconductor device of claim 1, wherein the field electrode dielectric is substantially U-shaped.

29. The semiconductor device of claim 1, wherein the opening of the field electrode dielectric is arranged in a region of the field electrode dielectric that faces in a direction of the junction.