Field effect semiconductor component and method for producing it

• US 9,391,192 B2
• Filed: 10/28/2014
• Issued: 07/12/2016
• Est. Priority Date: 10/30/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus, Bach, Karl-Heinz, Wood, Andrew Christopher Graeme
• Primary Examiner(s): Kusumakar, Karen
• Assistant Examiner(s): Bowen, Adam S
• Application Number:
  US14/525,398
• Publication Number:
  US 20150115353A1
• Time in Patent Office: 623 Days
• Field of Search: 257/330
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.

Claims

1. A field effect component, comprising a semiconductor body, which extends in an edge zone from a rear side as far as a surface of the semiconductor body, and which comprises a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the surface, as far as a semiconductor mesa top side arranged at a height above the surface, wherein the semiconductor body in a vertical cross section further comprises:

a drift region, which extends at least in the edge region as far as the surface and which is arranged partly in the semiconductor mesa; and

a body region, which is arranged at least partly in the semiconductor mesa and which forms a first pn junction with the drift region, said first pn junction extending between two sidewalls of the semiconductor mesa, wherein a vertical distance between the first pn junction and the semiconductor mesa top side varies in a horizontal direction and assumes a largest value in a central zone spaced apart from the two sidewalls, and wherein the largest value is at least 70% of the height.

2. The field effect component as claimed in claim 1, wherein the largest value is less than 200% of the height.

3. The field effect component as claimed in claim 1, wherein the body region has a second partial zone arranged in the central zone, said second partial zone forming a part of the first pn junction with the drift region and having a higher maximum dopant concentration than a first partial zone adjoining the second partial zone.

4. The field effect component as claimed in claim 1, wherein the first pn junction in the vertical cross section is either mirror-symmetrical relative to a vertical axis or asymmetrical with respect thereto.

5. The field effect component as claimed in claim 1, wherein the semiconductor mesa in the vertical cross section further has a source region, which is arranged on the body region and which forms a second pn junction with the body region.

6. The field effect component as claimed in claim 5, in the vertical cross section further comprising a gate dielectric zone arranged on at least one of the sidewalls, a gate electrode arranged on the gate dielectric zone, a source metallization arranged on the semiconductor body and in ohmic contact with the body region and the source region, and/or a drain metallization arranged on the rear side and in ohmic contact with the drift region.

7. The field effect component as claimed in claim 6, wherein the source metallization and the gate electrode are arranged above the surface.

8. The field effect component as claimed in claim 6, wherein the semiconductor body further comprises a side face extending between the rear side and the surface, and at least one edge termination structure arranged between the semiconductor mesa and the side face in a plan view.

9. The field effect component as claimed in claim 6, further comprising a shallow trench extending in the central zone from the semiconductor mesa top side right into the body region and/or as far as the first partial zone of the body region.

10. The field effect component as claimed in claim 1, wherein the semiconductor body has a multiplicity of semiconductor mesas in an active zone.

11. The field effect component as claimed in claim 10, in the active region further comprising a temperature sensor, a current sensor and/or a gate finger.

12. The field effect component as claimed in claim 10, in the active zone further comprising a further semiconductor mesa comprising a body region, which forms a pn junction with the drift region, wherein the body region of the further semiconductor mesa does not extend into the drift region as deeply as the body region of the semiconductor mesa in the vertical direction.

13. A field effect component, comprising a semiconductor body, which extends in an edge zone from a rear side as far as a surface and which comprises a semiconductor mesa, which extends in a vertical direction, which is parallel to a normal vector of the rear side and/or a normal vector of the surface, as far as a semiconductor mesa top side arranged above the surface, wherein the semiconductor body in a vertical cross section further comprises:

a drift region, which extends at least in the edge zone as far as the surface and which is arranged partly in the semiconductor mesa; and

a body region, which is arranged at least partly in the semiconductor mesa and which comprises two first partial zones, each adjoining one of two sidewalls of the semiconductor mesa, and a second partial zone arranged between the two first partial zones, wherein the two first partial zones and the second partial zone form a first pn junction with the drift region, said first pn junction extending between the two sidewalls of the semiconductor mesa, wherein the second partial zone extends into the drift region vertically more deeply than the two first partial zones, and wherein the second partial zone has a greater maximum dopant concentration than the two first partial zones.

14. The field effect component as claimed in claim 13, wherein a maximum vertical first distance between the semiconductor mesa top side and a first section of the first pn junction, which is formed between one of the two first partial zones and the drift region, is less than a vertical distance between the semiconductor mesa top side and the surface, and/or wherein a maximum vertical second distance between the semiconductor mesa top side and a second section of the first pn junction, which is formed between the second partial zone and the drift region, is in a range of 80% to 150% of the vertical distance.

15. A method for producing a field effect component, comprising:

providing a wafer, comprising a first semiconductor layer of a first conduction type, a second semiconductor layer of a second conduction type, which is arranged on the first semiconductor layer and which forms a first pn junction with the first semiconductor layer, and a third semiconductor layer, which is arranged on the second semiconductor layer and which forms a second pn junction with the second semiconductor layer and extends as far as a top side of the wafer;

forming a mesa mask on the top side of the wafer with a plurality of openings;

etching the wafer through the mesa mask, thus giving rise to deep trenches and semiconductor mesas arranged between the deep trenches, wherein the deep trenches extend right into the first semiconductor layer; and

implanting dopants of the first conduction type into at least one semiconductor zone adjoining the first pn junction.

16. The method as claimed in claim 15, further comprising forming insulated gate electrodes in at least some of the deep trenches, and/or forming shallow trenches from the top side into the semiconductor mesas.

17. The method as claimed in claim 15, further comprising separating the wafer into semiconductor components along some of the deep trenches.

18. The method as claimed in claim 15, further comprising a heat-treatment act, wherein the wafer with first pn junction and second pn junction parallel to one another is provided, and wherein the method is performed in such a way that after the heat-treatment act the first pn junction extends into the first semiconductor layer vertically more deeply in a central zone in at least one of the semiconductor mesas than at sidewalls of the at least one semiconductor mesa.

19. The method as claimed in claim 18, wherein the method is performed in such a way that the first semiconductor layer outside the semiconductor mesas forms a first surface situated at a vertical distance from the top side, wherein a vertical first distance between the top side and a first section of the first pn junction, said first section adjoining a sidewall of one of the semiconductor mesas, is less than a vertical second distance between the top side and a second section of the first pn junction, which adjoins the first section of the first pn junction, and which is in a range of 80% to 150% of the vertical distance between the top side and the first surface.

20. The method as claimed in claim 15, wherein the method is performed in such a way that the dopant concentration is increased in at least one of the semiconductor mesas in a central zone above the first pn junction, said central zone being spaced apart from sidewalls of the at least one semiconductor mesa.