High voltage vertical FPMOS fets
First Claim
1. A semiconductor power device disposed in a semiconductor substrate, comprising:
- trenches having defined widths formed at defined intervals perpendicular to and across a top portion of the semiconductor substrate extending laterally across the substrate and extending into an epitaxial layer;
base regions located outside the trenches;
long trench source electrodes inside the trenches; and
shorter gate electrodes inside the trenches positioned between the trench source electrodes and the base regions and generally parallel to the trench source electrodes, with an effective capacitance along their length from top region near the surface to bottom region towards the trench bottom, whereinthe distance between the trench source electrode surfaces and the gate electrode surfaces is larger at the top region than that at the bottom region.
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Accused Products
Abstract
Semiconductor power devices such as vertical FPMOS are described preferably having a plurality of trenches formed at a top portion of a semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction. Each trench has sidewalls generally perpendicular to a longitudinal direction of the trench and extending downward from a top surface to a trench bottom. Gate electrodes and source electrodes are positioned in the trenches with controlled spacing between their surfaces to achieve increased capacitance between them at increasing depth from the top surface. This provides higher frequency performance at higher power levels while improving tolerance to higher voltage.
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Citations
20 Claims
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1. A semiconductor power device disposed in a semiconductor substrate, comprising:
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trenches having defined widths formed at defined intervals perpendicular to and across a top portion of the semiconductor substrate extending laterally across the substrate and extending into an epitaxial layer; base regions located outside the trenches; long trench source electrodes inside the trenches; and shorter gate electrodes inside the trenches positioned between the trench source electrodes and the base regions and generally parallel to the trench source electrodes, with an effective capacitance along their length from top region near the surface to bottom region towards the trench bottom, wherein the distance between the trench source electrode surfaces and the gate electrode surfaces is larger at the top region than that at the bottom region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A vertical FPMOS having high voltage resistance without peripheral trench structure, comprising:
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a semiconductor substrate with an epitaxial layer, parallel trenches of defined widths at defined intervals across a top portion of the semiconductor substrate extending laterally across the substrate and extending into the epitaxial layer wherein the defined trench widths and the defined intervals between trenches are at a ratio of 1.0 to 2.5 respectively; base regions located outside and near the tops of the trenches; source electrodes inside the trenches; and gate electrodes inside the trenches positioned between the source electrodes and the base regions, wherein the location and doping of base and epitaxial regions are arranged to provide uniform expansion of the depletion layer, thereby providing high voltage resistance, and wherein the trench source electrode and trench gate electrode surfaces are positioned closer to each other at increasing depth in the trench. - View Dependent Claims (19, 20)
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Specification