High voltage vertical FPMOS fets

• US 9,391,194 B1
• Filed: 06/19/2015
• Issued: 07/12/2016
• Est. Priority Date: 06/19/2015
• Status: Active Grant

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: Fukunaga, Shunsuke
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): Jefferson, Quovaunda V
• Application Number:
  US14/744,183
• Time in Patent Office: 389 Days
• Field of Search: 257/330
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor power devices such as vertical FPMOS are described preferably having a plurality of trenches formed at a top portion of a semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction. Each trench has sidewalls generally perpendicular to a longitudinal direction of the trench and extending downward from a top surface to a trench bottom. Gate electrodes and source electrodes are positioned in the trenches with controlled spacing between their surfaces to achieve increased capacitance between them at increasing depth from the top surface. This provides higher frequency performance at higher power levels while improving tolerance to higher voltage.

Claims

1. A semiconductor power device disposed in a semiconductor substrate, comprising:

trenches having defined widths formed at defined intervals perpendicular to and across a top portion of the semiconductor substrate extending laterally across the substrate and extending into an epitaxial layer;

base regions located outside the trenches;

long trench source electrodes inside the trenches; and

shorter gate electrodes inside the trenches positioned between the trench source electrodes and the base regions and generally parallel to the trench source electrodes, with an effective capacitance along their length from top region near the surface to bottom region towards the trench bottom, wherein

the distance between the trench source electrode surfaces and the gate electrode surfaces is larger at the top region than that at the bottom region.

2. The semiconductor power device of claim 1, wherein the distance between the trench source electrode surfaces and the gate electrode surfaces decreases from the top region to the bottom region respectively.

3. The semiconductor power device of claim 1, wherein the trench gate electrodes are angled in towards the trench center with increasing depth in the trench.

4. The semiconductor power device of claim 1, wherein the trench source electrode is thicker at a deeper region below the gate electrodes.

5. The semiconductor power device of claim 3, wherein the thicker region of the source electrode starts at a depth that is below the gate electrode by a distance equal to at least half of the gate electrode thickness.

6. The semiconductor power device of claim 1, wherein the thickness of the trench source electrode parallel to the gate electrodes increases with increasing depth in the trench region at the location of the gate electrodes.

7. The semiconductor device of claim 1, wherein the thickness of the trench source electrode parallel to the gate electrodes increases with increasing depth in the trench region at the location of the gate electrodes and the gate electrode surfaces protrude closer to the center of the trench with increasing depth in the trench.

8. The semiconductor power device of claim 1, wherein the base dopant concentration is between 5×

10E16 to 5×

10E17 per cubic centimeter.

9. The semiconductor power device of claim 1, wherein the epitaxial layer has a dopant concentration of between 1.2E16 to 1.8E16 N−

per cubic centimeter.

10. The semiconductor power device of claim 3, wherein the epitaxial layer has a dopant concentration of between 1.2E16 to 1.8E16 N−

per cubic centimeter.

11. The semiconductor power device of claim 1, lacking a peripheral trench structure.

12. The semiconductor power device of claim 1, wherein the trench source electrodes are centered in the trenches, and extend at least mostly to the bottom of the trenches.

13. The semiconductor power device of claim 1, wherein the gate electrodes are between the trench source electrodes and the trench walls, and extend only partially into the trenches adjacent the base regions.

14. The semiconductor power device of claim 13, wherein the base regions are at the top of the epitaxial layer and extend down as far as the gate electrodes.

15. The semiconductor power device of claim 1, wherein the trench widths are approximately 1.5 microns.

16. The semiconductor power device of claim 10, wherein the spacing between trenches is approximately 1.7 microns.

17. The semiconductor power device of claim 1, having depletion regions along the trenches that expand uniformly with applied voltage.

18. A vertical FPMOS having high voltage resistance without peripheral trench structure, comprising:

a semiconductor substrate with an epitaxial layer,

parallel trenches of defined widths at defined intervals across a top portion of the semiconductor substrate extending laterally across the substrate and extending into the epitaxial layer wherein the defined trench widths and the defined intervals between trenches are at a ratio of 1.0 to 2.5 respectively;

base regions located outside and near the tops of the trenches;

source electrodes inside the trenches; and

gate electrodes inside the trenches positioned between the source electrodes and the base regions, wherein

the location and doping of base and epitaxial regions are arranged to provide uniform expansion of the depletion layer, thereby providing high voltage resistance, and

wherein the trench source electrode and trench gate electrode surfaces are positioned closer to each other at increasing depth in the trench.

19. The vertical FPMOS of claim 18, wherein the base dopant concentration is between 5×

10E16 to 5×

10E17 per cubic centimeter and wherein the N-epitaxial layer has a dopant concentration of between 1.2E16 to 1.8E16 per cubic centimeter.

20. The vertical FPMOS of claim 18, lacking a peripheral trench structure.