FinFETs having strained channels, and methods of fabricating finFETs having strained channels

• US 9,391,200 B2
• Filed: 06/18/2014
• Issued: 07/12/2016
• Est. Priority Date: 06/18/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Liu, Qing, Cai, Xiuyu, Xie, Ruilong, Yeh, Chun-chen
• Primary Examiner(s): Feeney, Brett
• Assistant Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US14/308,045
• Publication Number:
  US 20150372140A1
• Time in Patent Office: 755 Days
• US Class Current: 1/1
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G10L 15/16 using artificial neural networks
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/365 Planar doping, e.g. atomic-plane doping, delta-doping
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 : the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/13067 : FinFET, source/drain region shapes fins on the silicon surface

Abstract

Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Claims

1. A method for forming fins of a finFET, the method comprising:

forming one or more spacer layers over a fin including a semiconductor fin having a first height;

forming a planarized layer over the one or more spacer layers, the planarized layer being etch selective relating to the spacer layers;

recessing the planarized layer to a level between a bottom of the semiconductor fin and a top of the semiconductor fin;

etching the one or more spacer layers in a region adjacent the fin to expose at least a portion of the fin above a second height that is less than the first height, said etching of the one or more spacer layers being self-limited at the second height by the level of the recessed planarized layer;

removing the recessed planarized layer; and

etching the exposed portion of the fin to remove a portion of the semiconductor fin to a height determined, at least in part, by a top surface of the previously etched at least one of the one or more spacer layers at the second height.

2. The method of claim 1, wherein the etching of the exposed portion of the fin is self-limited by at least a level of the top surface of the previously etched at least one of the one or more spacer layers and by a width of an opening defined by the fin.

3. The method of claim 2, wherein the width of the semiconductor fin is between approximately 3 nm and approximately 10 nm.

4. The method of claim 1, wherein etching of the exposed portion of the fin comprises etching the exposed portion of the fin to approximately said top surface of the previously etched at least one of the one or more spacer layers.

5. The method of claim 1, wherein recessing the planarized layer comprises:

performing a timed etch of the planarized layer to etch back a top surface of the planarized layer to said level between the bottom of the semiconductor fin and the top of the semiconductor fin.

6. The method of claim 1, further comprising forming the one or more spacer layers covering first layer as a spacer layer at the fin and covering a gate conductor for the fin.

7. The method of claim 6, wherein the one or more spacer layers comprise a nitride layer and wherein etching the one or more spacer layers further comprises etching the nitride layer at the gate conductor to form gate spacers.

8. The method of claim 1, wherein forming the one or more spacer layers comprises:

conformally depositing a spacer layer over the fin to a thickness between approximately 5 nm and approximately 10 nm.

9. The method of claim 8, further comprising forming a gate spacer layer for a gate structure of the finFET in a same deposition step in which the spacer layer is deposited over the fin.

10. The method of claim 1, wherein etching the exposed portion of the fin comprises etching the semiconductor fin at source and drain regions of the finFET, and further comprising growing strain-inducing material on the semiconductor fin at the source and drain regions.

11. The method of claim 10, wherein a lattice parameter of the strain-inducing material differs from a lattice parameter of the semiconductor fin.

12. The method of claim 10, wherein the strain-inducing material imparts a strain in a channel of the finFET.

13. The method of claim 10, wherein the semiconductor fin is formed from bulk silicon and the strain-inducing material comprises one of silicon germanium and silicon carbide.

14. The method of claim 1, wherein the method further comprises forming a conformal insulating layer on the semiconductor fin prior to forming said one or more spacer layers, and wherein etching the one or more spacer layers comprises etching the conformal insulating layer to expose said portion of the semiconductor fin.

15. The method of claim 14, wherein the conformal insulating layer forms a gate insulator for the finFET.

16. The method of claim 1, wherein the planarized layer comprises an organic planarization layer.

17. A method for forming a finFET, comprising:

forming a fin structure including a semiconductor fin formed from a semiconductor layer of a silicon on insulator substrate, wherein the fin structure has a first fin height;

forming a gate structure over a channel region of the fin structure;

forming a spacer layer over the gate structure and the fin structure;

forming a planarized layer over the spacer layer, the planarized layer being etch selective relative to the spacer layer;

recessing the planarized layer to a top surface at a level between a bottom of the fin structure and a top of the fin structure;

etching the spacer layer to expose an upper portion of the fin structure, said etching of the spacer layer using the top surface of the recessed planarizing layer to self-limit the etching of the spacer layer to stop at a level approximately at a top surface of the spacer layer adjacent to the fin structure;

removing the planarizing layer;

etching the semiconductor fin of the fin structure to reduce the fin structure to a second fin height, the second fin height being less than the first fin height, so that sides of a lower portion of the fin structure remain covered by the etched spacer layer, said etching of the semiconductor fin using said etched spacer layer to self-limit the etching of the fin structure to stop at a level approximately at the top surface of the spacer layer;

wherein a channel region of the fin structure remains at the first fin height under the gate structure; and

epitaxially growing a source region and a drain region on exposed surfaces of the etched semiconductor fin adjacent the channel region.

18. The method of claim 17, further comprising depositing an oxide layer over the semiconductor fin;

and wherein forming the spacer layer comprises depositing the spacer layer over the oxide layer.

19. The method of claim 17, wherein a lattice parameter of the epitaxially grown source region and drain region differs from a lattice parameter of the semiconductor fin.

20. The method of claim 17, wherein the epitaxially grown source region and drain region impart a strain on the channel region.

21. The method of claim 17, wherein etching the spacer layer forms a spacer on side walls of the gate structure.