Semiconductor device

• US 9,391,209 B2
• Filed: 09/12/2013
• Issued: 07/12/2016
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Godo, Hiromichi, Arai, Yasuyuki, Okamoto, Satohiro, Terashima, Mari, Nishida, Eriko, Sugao, Junpei
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US14/024,962
• Publication Number:
  US 20140014954A1
• Time in Patent Office: 1,034 Days
• Field of Search: 257/40, 257/43, 257/59, 257/72, 257/258
• US Class Current: 1/1
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to provide a semiconductor device including an oxide semiconductor in which miniaturization is achieved while favorable characteristics are maintained. The semiconductor includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, and an insulating layer provided in contact with the oxide semiconductor layer. A side surface of the oxide semiconductor layer is in contact with the source electrode or the drain electrode. An upper surface of the oxide semiconductor layer overlaps with the source electrode or the drain electrode with the insulating layer interposed between the oxide semiconductor layer and the source electrode or the drain electrode.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer on and in direct contact with an insulating surface;

an insulating layer over the oxide semiconductor layer and in direct contact with the insulating surface, the insulating layer comprising an opening formed from a top surface to a bottom surface of the insulating layer;

an electrode in electrical contact with the oxide semiconductor layer in the opening;

a gate electrode overlapping with the oxide semiconductor layer;

a sidewall insulating layer covering a side surface of the gate electrode, the sidewall insulating layer being formed from a first layer and the insulating layer being formed from a second layer distinct from the first layer; and

a gate insulating layer between the oxide semiconductor layer and the gate electrode,

wherein the electrode is in direct contact with the sidewall insulating layer, and

wherein the electrode is in direct contact with and covers a top region of the insulating surface.

2. The semiconductor device according to claim 1, wherein the gate electrode is provided over the oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is provided over the gate electrode.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium and zinc.

5. The semiconductor device according to claim 1,

wherein the electrode comprises a first conductive layer and a second conductive layer having higher resistance than the first conductive layer, and

wherein the second conductive layer is in direct contact with the oxide semiconductor layer.

6. The semiconductor device according to claim 5, wherein a thickness of the second conductive layer is greater than or equal to 5 nm and less than or equal to 15 nm.

7. The semiconductor device according to claim 5, wherein the second conductive layer comprises a nitride of a metal.

8. The semiconductor device according to claim 1,

wherein the gate electrode is over the oxide semiconductor layer, and

wherein the insulating layer covers the gate electrode.

9. A semiconductor device comprising:

an oxide semiconductor layer on and in direct contact with an insulating surface;

an insulating layer over the oxide semiconductor layer and in direct contact with the insulating surface, the insulating layer comprising a first opening and a second opening each formed from a top surface to a bottom surface of the insulating layer;

a first electrode and a second electrode each in electrical contact with the oxide semiconductor layer, and totally filling the first opening and the second opening, respectively;

a gate electrode overlapping with the oxide semiconductor layer;

sidewall insulating layers covering two side surfaces of the gate electrode, the sidewall insulating layers being formed from a first layer and the insulating layer being formed from a second layer distinct from the first layer; and

a gate insulating layer between the oxide semiconductor layer and the gate electrode,

wherein the first electrode and the second electrode are each in direct contact with one of the sidewall insulating layers, and

wherein the first electrode and the second electrode are in direct contact with and cover a top region of the insulating surface.

10. The semiconductor device according to claim 9, wherein the gate electrode is provided over the oxide semiconductor layer.

11. The semiconductor device according to claim 9, wherein the oxide semiconductor layer is provided over the gate electrode.

12. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises indium and zinc.

13. The semiconductor device according to claim 9,

wherein the first electrode comprises a first conductive layer and a second conductive layer having higher resistance than the first conductive layer, and

wherein the second conductive layer is in direct contact with the oxide semiconductor layer.

14. The semiconductor device according to claim 13, wherein a thickness of the second conductive layer is greater than or equal to 5 nm and less than or equal to 15 nm.

15. The semiconductor device according to claim 13, wherein the second conductive layer comprises a nitride of a metal.

16. The semiconductor device according to claim 9,

wherein the gate electrode is over the oxide semiconductor layer, and

wherein the insulating layer covers the gate electrode.

17. The semiconductor device according to claim 9,

wherein, when seen in a cross-section taken along a length direction of a channel formation region of the oxide semiconductor layer, a distance separating the two openings is shorter than a distance separating the two side surfaces of the gate insulating layer.

18. A semiconductor device comprising:

an oxide semiconductor layer on and in direct contact with an insulating surface;

an insulating layer with a flat top surface over the oxide semiconductor layer and in direct contact with the insulating surface, the insulating layer comprising a first opening and a second opening each formed from the flat top surface to a bottom surface of the insulating layer;

a first electrode and a second electrode each in direct contact with the oxide semiconductor layer, and totally filling the first opening and the second opening, respectively;

a gate electrode overlapping with the oxide semiconductor layer;

a first sidewall insulating layer and second sidewall insulating layer each covering one of two side surfaces of the gate electrode, the first and the second sidewall insulating layers being formed from a first layer and the insulating layer being formed from a second layer distinct from the first layer; and

a gate insulating layer between the oxide semiconductor layer and the gate electrode,

wherein the first electrode and the second electrode are each in direct contact with one of the sidewall insulating layers, and

wherein the first electrode and the second electrode are in direct contact with and cover a top region of the insulating surface.

19. The semiconductor device according to claim 18,

wherein the gate electrode is over the oxide semiconductor layer, and

wherein the insulating layer covers the gate electrode.

20. The semiconductor device according to claim 18,

wherein, when seen in a cross-section taken along a length direction of a channel formation region of the oxide semiconductor layer, a distance separating the two openings is shorter than a distance separating two exterior side surfaces of the two sidewall insulating layers.

21. A semiconductor device comprising:

an oxide semiconductor layer on and in direct contact with an insulating surface;

an insulating layer over the oxide semiconductor layer and in direct contact with the insulating surface, the insulating layer comprising an opening formed from a top surface to a bottom surface of the insulating layer;

an electrode in electrical contact with the oxide semiconductor layer in the opening;

a gate electrode overlapping with the oxide semiconductor layer;

a sidewall insulating layer covering a side surface of the gate electrode, the sidewall insulating layer being formed from a first layer and the insulating layer being formed from a second layer distinct from the first layer; and

a gate insulating layer between the oxide semiconductor layer and the gate electrode,

wherein the electrode is in direct contact with the sidewall insulating layer.

22. A semiconductor device comprising:

an insulating surface;

an oxide semiconductor layer on the insulating surface;

first and second conductive layers on and in electrical contact with first and second portions of the oxide semiconductor layer, respectively;

a third conductive layer overlapping a third portion of the oxide semiconductor layer, the third portion being between the first and the second portions;

a first insulating layer covering a side surface of the third conductive layer and interposed between the third conductive layer and the first conductive layer;

an interlayer on the insulating surface and in direct contact with side edges of the first and the second conductive layers,

wherein the first insulating layer is interposed between the interlayer and the side surface of the third conductive layer, and

wherein the interlayer is not interposed between a portion of the first conductive layer and a bottom portion of the third conductive layer.

23. The semiconductor device according to claim 22,

wherein the first insulating layer overlaps a space separating the first and the third portions of the oxide semiconductor layers.

24. The semiconductor device according to claim 22, further comprising a second insulating layer between the oxide semiconductor layer and the third conductive layer,

wherein the first insulating layer and the second insulating layer are distinct from each other.

25. The semiconductor device according to claim 22,

wherein a cross section of the semiconductor device taken along a line going from the first conductive layer to the second conductive layer shows that the first conductive layer is interposed between a bottom portion of the first insulating layer and the interlayer and not interposed between a top portion of the first insulating layer and the interlayer.

26. A semiconductor device comprising:

an insulating surface;

an oxide semiconductor layer on the insulating surface;

first and second conductive layers on and in electrical contact with first and second portions of the oxide semiconductor layer, respectively;

a third conductive layer overlapping a third portion of the oxide semiconductor layer, the third portion being between the first and the second portions;

a first insulating layer covering a side surface of the third conductive layer and interposed between the third conductive layer and the first conductive layer;

an interlayer on the insulating surface and in direct contact with side edges of the first and the second conductive layers,

wherein the first insulating layer is interposed between the interlayer and the side surface of the third conductive layer, and

wherein the first insulating layer is in direct contact with the first conductive layer.

27. The semiconductor device according to claim 26,

wherein the first insulating layer overlaps a space separating the first and the third portions of the oxide semiconductor layers.

28. The semiconductor device according to claim 26, further comprising a second insulating layer between the oxide semiconductor layer and the third conductive layer,

wherein the first insulating layer and the second insulating layer are distinct from each other.

29. The semiconductor device according to claim 26,

wherein a cross section of the semiconductor device taken along a line going from the first conductive layer to the second conductive layer shows that the first conductive layer is interposed between a bottom portion of the first insulating layer and the interlayer and not interposed between a top portion of the first insulating layer and the interlayer.