Hardware-embedded key based on random variations of a stress-hardened inegrated circuit

• US 9,391,617 B2
• Filed: 05/08/2013
• Issued: 07/12/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mathew, Sanu K., Parker, Rachael J., Krishnamurthy, Ram K.
• Primary Examiner(s): Owens, Douglas W
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US13/889,849
• Publication Number:
  US 20140266297A1
• Time in Patent Office: 1,161 Days
• Field of Search: 326 9- 10, 326 14- 15, 326 59- 60, 326 93- 95, 326/98
• US Class Current: 1/1
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters

Abstract

An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.

Claims

1. A method, comprising:

repeatedly activating a first integrated circuit (IC) cell of an IC device, wherein the first IC cell is designed to resolve from an unstable output state to any one of multiple output states with equal probability, and wherein the activating includes,

pre-charging the first IC cell to the unstable output state, and

enabling the first IC cell to resolve from the unstable output state to one of the multiple output states based on random variations within the IC device; and

determining a measure of stability for the first IC cell based on the post-activation output states of the first IC cell.

2. The method of claim 1, wherein the computing includes:

for each of n activations of the first IC cell, incrementing a count if the corresponding output state corresponds to a first logic state, and maintaining the count if the output state corresponds to a second logic state;

determining a difference between the count and n, after the n activations of the first IC cell; and

computing the measure of stability for the first IC cell based on the difference.

3. The method of claim 1, wherein the first IC cell includes first and second devices, and wherein:

the pre-charging includes pre-charging outputs of the first and second devices to states that are incompatible with one another,

the enabling includes delaying enabling of one of the first and second devices relative to the other one of the first and second devices;

the method further includes identifying a first one of the multiple post-activation output states as a pre-determined output state of the first IC cell based on the post-activation output states of the first IC cell, wherein the pre-detemnned output state of the first IC cell depends on variations within the IC device; and

the computing includes computinq the measure of stability for the first IC cell based on a delay for which the post-activation output state of the first IC cell changes from the pre-determined output state to another one of the multiple post-activation output states.

4. The method of claim 3, further including:

stress programming the first IC cell to change the pre-determined output state to another one of the post-activation output states.

5. The method of claim 4, wherein the stress programming includes:

configuring the first IC cell to turn-on a weaker one of first and second devices and to turn-off a stronger one of the first and second devices while a stress-condition is applied to the first IC cell.

6. The method of claim 1, wherein the IC device includes an array of IC cells, including the first IC cell, the method further including:

selecting a subset of the IC cells based on corresponding measures of stability;

for each IC cell of the subset, identifying one of the multiple post-activation output states as a pre-determined output state of the respective IC cell based on the post-activation output states of the respective IC cell, wherein the predetermine output states of the subset of IC cells is determined by the random variations within the IC device; and

configuring the IC device to provide the pre-determined output states of the subset of IC cells as a key upon activation of the subset of IC cells.

7. An integrated circuit (IC) device, comprising:

an array of IC cells, each designed to resolve from an unstable output state to one of multiple post-activation output states with equal probability upon activation; and

control circuitry to activate the IC cells, including to pre-charge the IC cells to the unstable output state, and to enable each of the IC cells to resolve from the unstable output state to a pre-determined one of the multiple post-activation stable output states, wherein the pre-determined post-activation output states of the IC cells are determined by random variations within the IC device;

wherein the IC device is configured to provide the pre-determined post-activation output states of the IC cells as a key.

8. The IC device of claim 7, wherein:

the a first one of the IC cells includes first and second devices to control an output of the first IC cell;

the first and second devices are designed to have identical strengths;

the strengths of the first and second devices differ from one another due to the random variations within the IC device; and

the pre-determined post-activation output state of the first IC cell is determined by a stronger one of the first and second devices.

9. The IC device of claim 8, wherein the control circuitry is configured to:

pre-charge a node of each of the first and second devices to states that are incompatible with one another; and

enable the first and second devices to permit the node of one of the first and second devices to resolve to a state that is compatible with the node of the other one of the first and second devices.

10. The IC device of claim 7, wherein the first IC cell is stress-hardened to increase tolerance of the IC cells to one or more an environmental changes and instantaneous thermal noise.

11. A system, comprising:

an evaluation module to determine a measure of stability for a first IC cell of an IC device based on post-activation output states of the first IC cell;

wherein the IC device includes first control circuitry to activate the first IC cell, including to pre-charge the first IC cell to an unstable output state, and to enable the first IC cell to resolve from the unstable output state to a pre-determined one of multiple stable output states; and

wherein the first IC cell is designed to resolve from the unstable output state to any of the multiple stable output states with equal probability upon activation, and wherein the pre-determined output state is determined by random variations within the IC device.

12. The system of claim 11, wherein the evaluation module includes:

a counter to increment a count if the post-activation output state corresponds to a first logic state, and to maintain the count if the post-activation output state corresponds to a second logic state;

a comparator to determine a difference between the count and n, after n activations of the first IC cell; and

a decision module to determine the measure of stability based on the difference.

13. The system of claim 11, wherein the evaluation module is configured to controllably delay enablement of one of first and second devices of the first IC cell relative to the other, and to determine a measure of stability for the first IC cell based on a delay for which the post-activation output state of the first IC cell changes from the pre-determined output state to another state.

14. The system of claim 11, further including a stress-hardening module to configure the first IC cell to assert an output state other than the pre-determined output state while a stress-condition is applied to the first IC cell.

15. The system of claim 11, further including a stress-hardening module to configure the first IC cell to turn-on a weaker one of first and second devices of the first IC cell and to turn-off a stronger one of the first and second devices, while a stress-condition is applied to the first IC cell.

16. The system of claim 11, wherein the IC device includes an array of IC cells and corresponding control circuitry, including the first IC cell and the first control circuitry, and wherein the evaluation system is configured to,

determine measures of stability for the multiple IC cells,

select a subset of the IC cells based on corresponding measures of stability, and

configure the IC device to provide pre-determined output states of the selected subset of IC cells as a key upon activation of the selected IC cells.

17. A non-transitory computer-readable medium encoded with a computer program, including evaluation instructions to cause a processor to:

determine a measure of stability for a first IC cell of an IC device based on post-activation output states of the first IC cell;

wherein the IC device includes first control circuitry to activate the first IC cell, including to pre-charge the first IC cell to an unstable output state, and to enable the first IC cell to resolve from the unstable output state to a pre-determined one of multiple stable output states; and

wherein the first IC cell is designed to resolve from the unstable output state to any of the multiple stable output states with equal probability upon activation, and wherein the pre-determined output state is determined by random variations within the IC device.

18. The computer-readable medium of claim 17, wherein the evaluation instructions include instructions to cause the processor to:

for each of n activations of the IC cell, increment a count if the corresponding output state corresponds to a first logic state, and maintain the count if the output state corresponds to a second logic state;

determine a difference between the count and n, after the n activations of the first IC cell; and

determine a measure of stability for the IC cell based on the difference.

19. The computer-readable medium of claim 17, wherein the evaluation instructions include instructions to cause the processor to:

controllably delay the enabling of one of the first and second devices relative to the other; and

determine a measure of stability for the first IC cell based on a delay for which the post-activation output state of the first IC cell changes from the pre-determined output state to another state.

20. The computer-readable medium of claim 17, further including stress-hardening instructions to cause the processor to:

configure the first IC cell to assert an output state other than the pre-determined output state while a stress-condition is applied to the first IC cell.

21. The computer-readable medium of claim 17, further including stress-hardening instructions to cause the processor to:

configure the first IC cell to turn-on a weaker one of first and second devices of the first IC cell and to turn-off a stronger one of the first and second devices while a stress-condition is applied to the first IC cell.

22. The computer-readable medium of claim 17, wherein the IC device includes an array of IC cells, including the first IC cell, further including instructions to cause the processor to:

selecting a subset of the IC cells based on corresponding measures of stability; and

configure the IC device to provide pre-determined output states of the selected subset of IC cells as a key upon activation of the selected IC cells.

23. A system, comprising:

an integrated circuit (IC) device, including,

an array of IC cells, each designed to resolve from an unstable output state to any one of multiple stable output states with equal probability upon activation, and

control circuitry to activate the IC cells, including pre-charge circuitry to pre-charge each of the IC cells to the unstable output state and enable circuitry to enable each of the IC cells to resolve from the unstable output state to a corresponding pre-determined one of the multiple stable output states,

wherein the pre-determined output states are determined by random variations within the IC device, and

wherein the IC device is configured to provide the pre-determined output states of a sub-set of the IC cells as a key upon activation of the selected sub-set of IC cells; and

a processor and memory to receive the key from the IC device.

24. The system of claim 23, further including:

a user interface to present information from the processor; and

a communication system to interface between a communication network and one or more of the processor and the user interface.

25. The system of claim 24 configured as a portable telephone.

26. The system of claim 24, configured as a portable computer system.

27. The system of claim 24, wherein the processor and memory are configured to use the key as one or more of,

a Platform Root Key,

a High-Bandwidth Digital Content Protection (HDCP) key,

an Enhanced Privacy Identification (EPID) key, and

and an Advanced Access Content System (AACS) key.